EEPROM flash memory erasable line by line

• US 6,687,167 B2
• Filed: 08/20/2002
• Issued: 02/03/2004
• Est. Priority Date: 08/30/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Poles, Marco, Iezzi, David, Pasotti, Marco, De Sandre, Guido, Rolandi, Pier Luigi, Guaitini, Giovanni
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US10/225,513
• Publication Number:
  US 20030067804A1
• Time in Patent Office: 532 Days
• Field of Search: 365/189.09, 365/185.13, 365/185.14, 365/185.23, 365/185.28, 365/185.29
• US Class Current: 365/189.09
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.

Claims

1. An EEPROM flash memory capable of being erased line by line and comprising:

a matrix (MEM) of cells connected to each other by means of row lines and column lines,

row decoder circuits (DEC) comprising logic decoder units (DECx-z),

voltage level conversion units (LSHx-z) and interface logic stages (ILOG) between the level conversion units (LSHx-z) and the row lines of the matrix,

each interface stage comprising elementary row driving stages, each of which has inputs connected to corresponding outputs of the level conversion units (LSHx-z), an output connected to a row line (WL) and a first (SUPPLY_P) and a second (SUPPLY_N) supply voltage terminal and comprises a first branch comprising a first MOS transistor (P01) of a first type, connected with its source drain-path between the output (WL) and the first (SUPPLY_P) supply terminal and a second branch comprising a second MOS transistor (N01) of second type, connected with its source-drain path between the output (WL) and the second (SUPPLY_N) supply terminal, the gate terminals of the first and the second MOS transistor being two inputs of the elementary row driving stage,

characterized in that each elementary row pilot stage comprises;

in the first branch a first supplementary MOS transistor (N00) of the second type (n), connected with its source-drain path in series with the first MOS transistor (P01) and with its gate terminal connected to a first biasing terminal (NRM), and

in the second branch a second supplementary MOS transistor (P00) of the first type (p), connected with its source-drain path in series with the source-drain path of the second MOS transistor (N01) of the second type (n) and with its gate terminal connected to a second biasing terminal (GPMOS).

2. The memory in accordance with claim 1, wherein the second supply terminals (SUPPLY_N) of the elementary stages are connected to a common terminal.

3. The memory in accordance with claim 2, wherein each elementary row driving stage comprises a third MOS transistor (N02) of the second type connected with its source-drain path in parallel with the source-drain path of the second MOS transistor (n01) of the second type, the gate terminal of the third MOS transistor being connected, as a further input of the stage, to a corresponding output of the voltage level conversion unit (LSHx,y).

4. The memory in accordance with claim 3, wherein the elementary stages are connected pair by pair to the first supply terminal (SUPPLY_P) by means of the source-drain path of a fourth MOS transistor (P02) of the first type having its gate terminal connected, as a further input of the pair of elementary stages, to a corresponding output of the voltage level conversion unit (LSHx,y).

5. A method of reading, programming and erasing a memory comprising:

a matrix (MEM) of cells connected to each other by means of row lines and column lines,

row decoder circuits (DEC) comprising logic decoder units (DECx-z),

voltage level conversion units (LSHx-z) and interface logic stages (ILOG) between the level conversion units (LSHx-z) and the row lines of the matrix,

each interface stage comprising elementary row driving stages, each of which has inputs connected to corresponding outputs of the level conversion units (LSHx-z), an output connected to a row line (WL) and a first (SUPPLY_P) and a second (SUPPLY_N) supply voltage terminal and comprises a first branch comprising a first MOS transistor (P01) of a first type, connected with its source drain-path between the output (WL) and the first (SUPPLY_P) supply terminal and a second branch comprising a second MOS transistor (N01) of second type, connected with its source-drain path between the output (WL) and the second (SUPPLY_N) supply terminal, the gate terminals of the first and the second MOS transistor being two inputs of the elementary row driving stage,

wherein the polarizations of the elementary row driving stages during the phases or reading and programming a cell of a row are chosen in such a manner that the first and the second branch of the elementary row driving stage function, respectively, as a pull-up branch and a pull-down branch, and

wherein the polarizations of the elementary row driving stages during the phase of erasing a cell of a row are chosen in such a manner that the first and the second branch of the elementary row driving stage function, respectively, as a pull-down branch and a pull-up branch.

6. The method in accordance with claim 5, wherein the body regions of the first (N00) and the second (P00) supplementary MOS transistor during the reading and programming phases are biased to voltages that are, respectively, higher and lower than the voltages of their respective source regions.

7. An EEPROM memory array word line control circuit, comprising, for each of a plurality of word lines in the memory array:

a first pull circuit connected between each word line of the memory and a first voltage supply node, the first pull circuit including a first transistor of a first conductivity type;

a second pull circuit connected between each word line of the memory and a second voltage supply node, the second pull circuit including a second transistor of a second conductivity type;

wherein reading/programming of the certain word line is effectuated by biasing the first and second transistors high and relatively low, respectively, and configuring the first pull circuit for the certain word line as a pull-up and the second pull circuit for other word lines as a pull-down; and

wherein erasure of memory cells associated with only the certain word line is effectuated by biasing the first and second transistors to ground and configuring the first pull circuit as a pull-down for the certain word line and the second pull circuit for other word lines as a pull-up.

8. The circuit as in claim 7 wherein:

the first pull circuit further includes a third transistor of the second conductivity type; and

the second pull circuit further includes a fourth transistor of the first conductivity type;

wherein during reading/programming of the certain word line, the third and fourth transistors are biased to ground; and

wherein during erasure of only the certain word line, the third and fourth transistors are biased to a negative voltage and ground, respectively.

9. The circuit as in claim 7 wherein the first and second transistors each have body regions connected to their respective drain regions.

10. The circuit as in claim 7 wherein, during reading/programming of the certain word line, the first and second transistors are biased with their respective source-body junctions in direct conduction.

11. A method for operating an EEPROM memory array, wherein each of a plurality of word lines includes a first pull branch and second pull branch connected to the word line, comprising the steps of:

for reading/programming;

activating the first pull branch for only a certain one of the word lines as a pull-up and activating the second pull branches for the other word lines as pull-downs; and

for erasure;

activating the first pull branch for only the certain one of the word lines as a pull-down and activating the second pull branches for the other word lines as pull-ups.

12. The method as in claim 11 wherein, during reading/programming of the certain word line, a transistor in the first pull branch is biased with its source-body junction in direct conduction.

13. An EEPROM memory array word line control circuit, comprising, for each of a plurality of word lines in the memory array:

a first pull circuit connected to a word line; and

a second pull circuit connected to the word line;

wherein reading/programming of memory cells associated with a certain word line is effectuated by configuring the first pull circuit for the certain word line as a pull-up and the second pull circuit for other word lines as a pull-down; and

wherein erasure of memory cells associated with only the certain word line is effectuated by configuring the first pull circuit as a pull-down for the certain word line and the second pull circuit for other word lines as a pull-up.

14. The circuit as in claim 13 wherein:

the first and second pull circuits each include a transistor having its body region connected to its drain region.

15. The circuit as in claim 14 wherein, during reading/programming of the certain word line, the first and second transistors are biased with their respective source-body junctions in direct conduction.