System and method for ensuring operations of redundant signal paths in a communication system

• US 6,687,231 B1
• Filed: 11/30/1999
• Issued: 02/03/2004
• Est. Priority Date: 05/28/1999
• Status: Expired due to Fees

• Current Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Simmering, Marlin V., Rzonca, Richard Roger, Groote, Jan De, Czerwiec, Richard Marion, Wonterghem, Geert Van
• Primary Examiner(s): Ngo, Ricky
• Assistant Examiner(s): Swickhamer, Christopher M
• Application Number:
  US09/450,714
• Time in Patent Office: 1,526 Days
• Field of Search: 370/217, 370/218, 370/219, 370/220, 370/221, 370/225, 370/226, 370/227, 370/228, 370/401, 370/463, 370/395.1, 370/242-244
• US Class Current: 370/244
• CPC Class Codes: H04B 1/74 for increasing reliability, e.g. using redundant or spare channels or apparatus replacing by standby devices for amplifiers H03F1/52, H03F1/542
• CPC Class Codes: H04M 3/241 for stored program controlled exchanges

Abstract

A system and method for enhancing reliability in a communication system. In the system and method, redundant signal paths are continuously tested to determine if any faults are present while the operating signal paths are in use. If any faults are present in the redundant signal paths, they can be addressed while the operating circuits are still in use. This minimizes the chance that a switch from an operating signal path to a redundant signal path because of a fault in the operating circuit will result in downtime.

Claims

1. A method for a system including a plurality of line cards each having at least one encoder and each for receiving a first downstream signal and encoding to generate a respective subscriber downstream signal for sending to a respective subscriber, the method comprising:

receiving, in each line card, the first downstream signal from a first source over a first downstream signal path;

sending, from at least one line card, a first upstream signal to the first source over a first upstream path;

testing a second downstream path from a second source to the at least one line cards and a second upstream path from the at least one line cards to the second source; and

if a failure is detected along the first downstream signal path or the first upstream signal path and a failure is not detected along the second downstream signal path or the second upstream signal path, a second receiving step of receiving the first downstream signal from the second source,

wherein a multiplexing process is used to enable the line cards to share the first upstream signal path and the same multiplexing process is used to enable the line cards to share the second upstream signal path, so that the testing of the second upstream path occurs in synchronism with the sending of the first upstream signal by each respective line cards.

2. The method of claim 1 wherein the second source is part of a circuit card, and wherein testing includes generating a test upstream signal on the at least one line card in response to a test downstream signal received from the circuit card.

3. The method of claim 2, wherein the testing step comprises:

sending the test downstream signal from the second source to at least one of the line cards;

receiving the test downstream signal in at least one of the line cards;

generating the test upstream signal in the at least one line cards in response to the test downstream signal;

sending the test upstream signal to the circuit card; and

examining the test upstream signal received in the circuit card to determine it a failure has occurred.

4. The method of claim 3, wherein generating the test upstream signal includes generating a redundancy signal.

5. The method of claim 3, wherein the third signal includes a plurality of first digit positions, and generating the fourth signal includes generating the fourth signal to include a plurality of second digit positions, each second digit position corresponding to a respective first digit position.

6. A system for operating with a network, the system comprising:

a first circuit card for receiving from the network to generate a first signal;

a second circuit card for receiving from the network to generate the first signal;

a plurality of line cards;

a first upstream signal path, the first upstream signal path being for sending from the line cards to the first circuit card;

a second upstream signal path, the second upstream signal path being for sending from the line cards to the second circuit card;

wherein each line card includes

a multiplexor that generates a multiplexor output responsive either to the first signal from the first circuit card or the first signal from the second circuit card,

an encoder that;

encodes the multiplexor output to generate a respective second signal for sending to a respective subscriber,

a sender that sends on the second upstream signal path, at a time when the multiplexor is responsive to the first signal from the first circuit card, thereby testing the second upstream signal path.

7. The system of claim 6 further wherein the line cards share the first upstream signal path using a multiplexing process, and the sender in each line card includes logic to send on the second upstream signal path in synchronism with the multiplexing process.

8. The system of claim 6 further wherein the system generates respective fourth signals for each line card to grant each line card access to the first upstream signal path at a respective particular time, and the sender in each line card is responsive to one of the fourth signals.

9. The system of claim 6 wherein the sender in each line card includes a generator that generates a test upstream signal in response to a signal received from the second circuit card, to send the test upstream signal on the second upstream signal path.

10. The system of claim 6 wherein, the first source is on a first circuit card, the second source is on a second circuit card, and the system further including

a generator that sends a test downstream signal from the second circuit card;

a receiver that receives the test downstream signal on at least one of the line cards;

a generator that generates a test upstream signal in the at least one of the line cards, in response to the third test downstream signal;

a sender that sends the test upstream signal to the second circuit card; and

circuitry for analyzing the test upstream signal on the second circuit card.

11. The system of claim 10 wherein the generator that generates the test upstream signal includes logic that generates a redundancy signal.

12. The system of claim 10 wherein the test downstream signal includes a plurality of first digit positions, and the test upstream signal includes a plurality of second digit positions, each second digit position corresponding to a respective first digit position.

13. The system of claim 10 wherein the first upstream signal path includes a first plurality of parallel conductors, the second upstream signal path includes a second plurality of parallel conductors, the system further includes

a housing supporting the first and second plurality or conductors,

and each line card includes

a connector for mechanically coupling to the housing, the connector having a plurality of connector conductors for sending signals between the line card to the first and second plurality of conductors.

14. A system comprising:

a plurality of line cards each having at least one encoder and each for receiving a first downstream signal and encoding to generate a respective subscriber signal for sending to a respective subscriber;

means for receiving, in each line card, the first downstream signal from a first source over a first downstream signal path,

means for sending, from at least one line card, a first upstream signal to the first source over a first upstream path;

means for testing a second downstream path from a second source to the at least one line cards and a second upstream path from the at least one line cards to the second source;

means for receiving the first downstream signal from the second source if a failure is detected along the first downstream signal path or the first upstream signal path and a failure is not detected along the second downstream signal path or the second upstream signal path; and

means for multiplexing so that the line cards share the first upstream signal path and share the second upstream signal path, so that the testing of the second upstream path occurs in synchronism with the sending of the first upstream signal by each respective line cards.

15. The system of claim 14 wherein the second source is part of a circuit card, and wherein the means for receiving while testing includes a signal a generator responsive to a signal received from the circuit card.

16. The system of claim 15 wherein the means for testing comprises:

means for sending a test downstream signal from the second source to at least one of the line cards;

means for receiving the test downstream signal in at least one of the line cards;

means for generating a test upstream signal in the at least lone line cards in response to the test downstream signal;

means for sending the test upstream signal to the circuit card; and

means for examining the test upstream signal received in the circuit card to determine if a failure has occurred.

17. The system of claim 16 wherein the means for generating the test upstream signal includes a redundancy signal generator.

18. The system of claim 16 wherein the test downstream signal includes a plurality of first digit positions, and generating the test upstream signal includes a plurality of second digit positions, each second digit position corresponding to a respective first digit position.

19. The system of claim 16 wherein the second downstream signal path includes a plurality of parallel conductors, the system further includes

a housing supporting the plurality of parallel conductors, and each line card includes

a connector for mechanically coupling to the housing, the connector having a plurality of connector conductors for sending signals between the line card and the plurality of parallel conductors.