Method and apparatus for performing analog mode operations when receiving data and signaling tones in a wireless TDMA system

• US 6,687,314 B1
• Filed: 03/03/2000
• Issued: 02/03/2004
• Est. Priority Date: 03/03/2000
• Status: Expired due to Fees

• Current Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Subramanian, Suresh, Leonard, Eric David, Thomson, David James
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Kim, Kevin
• Application Number:
  US09/517,997
• Time in Patent Office: 1,432 Days
• Field of Search: 375/347, 375/285, 375/299, 375/357, 375/365, 375/324, 370/514, 370/442, 714/822
• US Class Current: 375/324
• CPC Class Codes: H04L 25/067 providing soft decisions, i.e. decisions together with an estimate of reliability H04L25/068 and H04L25/069 take precedence; sequence estimation techniques H04L25/03178
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/046 using a dotting sequence

Abstract

A method and apparatus are provided for use in a transceiver of a wireless system that enable analog mode operations to be performed using in-phase (I) and quadrature (Q) values. When operating in the analog mode, the apparatus comprises a processor that receives digital I, Q pairs relating to audio or data signals and performs FM demodulation to generate information content relating to the audio or data signals. When receiving data in the analog mode, the data is in a particular format.

Claims

1. An apparatus for receiving signals transmitted over a wireless network in an analog mode, the apparatus comprising:

first logic, the first logic receiving the transmitted signals, the first logic being configured to convert the transmitted signals into digital signals; and

second logic in communication with the first logic, the second logic being configured to convert the digital signals into a sequence of bits, wherein the sequence of bits corresponds to a particular group of the transmitted signals, and wherein the group of transmitted signals are transmitted a plurality of times, thereby causing the sequence of bits to be repeated a plurality of times, said sequence of bits corresponding to a binary radio link word (RLW), the RLW comprising a first field corresponding to said first set of said sequence of bits, a second field corresponding to a second set of said sequence of bits and a third field corresponding to a third set of said sequence of bits, the third set of said sequence of bits corresponding to a data message, wherein the second logic analyzes the first sequence of bits to determine whether or not the first sequence of bits represents a continuous waveform of a particular frequency, wherein if the second logic determines that the first sequence of bits represents the continuous waveform of the particular frequency, the second logic determines that a data message is being received, wherein the data message is represented by the third set of said sequence of bits, and wherein the second logic determines whether the first set of said sequence of bits represents the continuous waveform of the particular frequency by measuring an energy level associated with a waveform produced by the first set of said sequence of bits and by measuring a level of noise associated with the continuous waveform.

2. The apparatus of claim 1, wherein the transmitted signals are represented by analog in-phase (I) and quadrature phase (Q) cosine waves that have been summed for transmission, and wherein the first logic is configured to process the summed analog I and Q cosine waves to produce digital I and Q values, the second logic being configured to demodulate and decode the digital I and Q values to convert the digital I and Q values into said sequence of bits.

3. The apparatus of claim 1, wherein if the measured energy level exceeds a predetermined energy level threshold value and if the noise level exceeds a predetermined signal-to-noise-and-distortion (SINAD) ratio threshold level, the second logic determines a phase associated with the first set of said sequence of bits and utilizes the phase determination to perform clock recovery.

4. The apparatus of claim 3, wherein once the second logic has performed clock recovery, the second logic compares the second set of said sequence of bits with a stored, preselected sequence of bits to determine where a first bit cell of the third set of said sequence of bits begins.

5. The apparatus of claim 4, wherein once the second logic has determined where the first bit cell of the third set of said sequence of bits begins, the second logic decodes the third set of said sequence of bits.

6. The apparatus of claim 5, wherein the RLW corresponds to a particular group of the transmitted signals, wherein the particular group of the transmitted signals are transmitted a plurality of times, thereby causing the RLW to be repeated a plurality of times, the second logic evaluating each repeat of the RLW and producing a confidence factor for each bit of each RLW, each confidence factor being based on how closely a respective bit resembles a binary 1 or a binary 0 and on a signal strength associated with the respective bit, and wherein once the confidence factors have been produced for each bit of each repeat of the RLW, the second logic uses the confidence factors associated with each bit of each repeat to determine whether each bit is a binary 1 or a binary 0.

7. The apparatus of claim 6, wherein once the confidence factors have been produced for each bit for each repeat of the RLW, the confidence factors associated with any given bit are summed and the sums are compared to a predetermined threshold value to determine whether the bit corresponds to a binary 1 or a binary 0.

8. The apparatus of claim 7, wherein once each bit has been determined to be either a binary 1 or a binary 0, the second logic compares the binary bit values of the first and second sets of said sequence of bits to a pre-selected, stored set of bit values to determine the number of bit errors existing in the first and second sets of said sequence of bits, wherein once the second logic has determined the number of bit errors existing in the first and second sets of said sequence of bits, the second logic compares the number of bit errors to a bit-error threshold value to determine whether or not to abort message processing.

9. The apparatus of claim 1, wherein the first logic comprises a frequency converter and a digital down-converter and wherein the second logic comprises a digital signal processor (DSP).

10. The apparatus of claim 1, wherein the apparatus is comprised in a base station of the wireless network and wherein the transmitted signals correspond to messages being sent from a mobile unit to the base station of the wireless network.

11. An apparatus for receiving signals transmitted over a wireless network in an analog mode, the apparatus comprising:

first logic, the first logic receiving the transmitted signals, the first logic being configured to convert the transmitted signals into digital signals; and

second logic in communication with the first logic, the second logic being configured to convert the digital signals into a sequence of bits, wherein the sequence of bits corresponds to a particular group of the transmitted signals, and wherein the group of transmitted signals are transmitted a plurality of times, thereby causing the sequence of bits to be repeated a plurality of times, said sequence of bits comprising a first field corresponding to a first set of said sequence of bits, a second bit field corresponding to a second set of said sequence of bits and a third bit field corresponding to a third set of said sequence of bits, wherein the second logic analyzes the first set of said sequence of bits to determine whether or not the first set of said sequence of bits represents a continuous waveform of a particular frequency, wherein if the second logic determines that the first set of said sequence of bits represents the continuous waveform of the particular frequency, the second logic determines that a data message is being received, wherein the data message is represented by the third set of said sequence of bits.

12. The apparatus of claim 11, wherein the transmitted signals are represented by analog in-phase (I) and quadrature phase (Q) cosine waves that have been summed for transmission, and wherein the first logic is configured to process the summed analog I and Q cosine waves to produce digital I and Q values and to convert the digital I and Q values into said sequence of bits, the second logic being configured to demodulate and decode the digital I and Q values to convert the digital I and Q values into said sequence of bits.

13. The apparatus of claim 12, wherein once the second logic determines that a data message is being received, the second logic determines whether a signaling tone bit sequence representing a continuous waveform of a particular frequency has been received, the second logic determining whether the signaling tone bit sequence representing the continuous waveform of the particular frequency has been received by measuring an energy level associated with a waveform produced a sequence of bits being received, wherein if the second logic determines that the energy level exceeds a particular energy level threshold value, the second logic determines an amount of time that the threshold energy level has been continuously exceeded, wherein if the second logic determines that the threshold energy level has been exceeded for a particular amount of time, the second logic stores an indication that signaling tone has been detected.

14. The apparatus of claim 12, wherein the second logic evaluates each repeat of the RLW and produces a confidence factor for each bit of each RLW, each confidence factor being based on how closely a respective bit resembles a binary 1 or a binary 0 and on a signal strength associated with the respective bit, and wherein once the confidence factors have been produced for each bit of each repeat of the RLW, the second logic uses the confidence factors associated with each bit of each repeat to determine whether each bit is a binary 1 or a binary 0, wherein once each bit has been determined to be either a binary 1 or a binary 0, the second logic compares the binary bit values of the first and second sets of said sequence of bits to a pre-selected, stored set of bit values to determine the number of bit errors existing in the first and second sets of said sequence of bits, wherein once the second logic has determined the number of bit errors existing in the first and second sets of said sequence of bits, the second logic compares the number of bit errors to a bit-error threshold value to determine whether or not a data message has been received.

15. A method for receiving signals transmitted over a wireless network in an analog mode, the method comprising the steps of:

receiving the transmitted signals and converting the transmitted signals into digital signals;

converting the digital signals into a sequence of bits, wherein the sequence of bits corresponds to a particular group of the transmitted signals, and wherein the group of transmitted signals are transmitted a plurality of times, thereby causing the sequence of bits to be repeated a plurality of times;

analyzing the sequence of bits to determine whether or not a first set of the sequence of bits represents a continuous waveform of a particular frequency, said sequence of bits corresponding to a binary radio link word (RLW), the RLW comprising a first field corresponding to said first set of said sequence of bits, a second field corresponding to a second set of said sequence of bits and a third field corresponding to a third set of said sequence of bits, the third set of said sequence of bits corresponding to a data message, wherein the second logic analyzes the first sequence of bits to determine whether or not the first sequence of bits represents a continuous waveform of a particular frequency, wherein if the second logic determines that the first sequence of bits represents the continuous waveform of the particular frequency, the second logic determines that a data message is being received, wherein the data message is represented by the third set of said sequence of bits, and wherein the second logic determines whether the first set of said sequence of bits represents the continuous waveform of the particular frequency by measuring an energy level associated with a waveform produced by the first set of said sequence of bits and by measuring a level of noise associated with the continuous waveform; and

if a determination that the first set of the sequence of bits represents the continuous waveform of the particular frequency, making a determination that a data message is being received.

16. A method for receiving signals transmitted over a wireless network in an analog mode, the apparatus comprising:

receiving the transmitted signals and converting the transmitted signals into digital signals;

converting the digital signals into a sequence of bits, wherein the sequence of bits corresponds to a particular group of the transmitted signals, and wherein the group of transmitted signals are transmitted a plurality of times, thereby causing the sequence of bits to be repeated a plurality of times, said sequence of bits comprising a first field corresponding to a first set of said sequence of bits, a second bit field corresponding to a second set of said sequence of bits and a third bit field corresponding to a third set of said sequence of bits;

analyzing the first set of said sequence of bits to determine whether or not the first set of said sequence of bits represents a continuous waveform of a particular frequency;

if a determination is made that the first set of said sequence of bits represents the continuous waveform of the particular frequency, making a determination that a data message is being received, wherein the data message is represented by the third set of said sequence of bits.