Single chip VLSI implementation of a digital receiver employing orthogonal frequency division multiplexing

• US 6,687,315 B2
• Filed: 11/27/2001
• Issued: 02/03/2004
• Est. Priority Date: 02/18/1997
• Status: Expired due to Term

• Current Assignee: Chartoleaux KG LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Davies, David H., Alam, Dawood, Keevill, Peter A, Nolan, John M., Collins, Matthew J, Foxcroft, Thomas, Parker, Jonathan
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/995,011
• Publication Number:
  US 20030142764A1
• Time in Patent Office: 798 Days
• Field of Search: 375/132, 375/130, 375/134, 375/137, 375/140, 375/142, 375/324, 375/260, 375/356, 370/206, 370/208, 370/210, 370/491, 370/460, 370/500, 370/478, 370/343, 370/344
• US Class Current: 375/341
• CPC Class Codes: H04L 27/26524 Fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators in combination with other circuits for demodulation
• CPC Class Codes: H04L 27/2662 Symbol synchronisation
• CPC Class Codes: H04L 27/2678 using cyclostationarities, e.g. cyclic prefix or postfix

Abstract

The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Claims

1. A modulated multi-carrier receiver, comprising:

a demodulator accepting digitized data representing modulated multi-carrier symbols;

carrier recovery circuitry;

a microprocessor interface;

a Viterbi decoder;

channel estimation circuitry; and

an FFT processor, said carrier recovery circuitry, said microprocessor interface, said Viterbi decoder, said channel estimation circuitry, and said FFT processor being interlinked and implemented in a single chip to produce an output including demodulated video data.

2. The receiver of claim 1 wherein the output complies with a digital video standard.

3. The receiver of claim 1 wherein the produced output includes MPEG compliant video data.

4. The receiver of claim 3 wherein the demodulator demodulates COFDM symbols.

5. The receiver of claim 4 wherein the produced output includes MPEG-2 compliant video data.

6. The receiver of claim 1 further comprising:

an I/Q demodulator;

timing recovery circuitry;

a reed-solomon decoder;

a symbol deinterleaver;

a clock source for controlling an analog-to-digital converter; and

an automatic gain control signal generator.

7. The receiver of claim 1 wherein recovered carriers from the carrier recovery circuitry that fail to meet predetermined quality standards are ignored by the Viterbi decoder.

8. The receiver of claim 7 wherein the recovered carriers have an interpolated channel response and the predetermined quality standard is a function of the interpolated channel response.

9. The receiver of claim 1 wherein the carriers failing to meet a defined strength threshold are flagged, and the Viterbi decoder is used to decode data from flagged carriers.

10. The receiver of claim 9 wherein the strength threshold is approximately 0.2 of a detected mean value.

11. The receiver of claim 9 wherein the strength threshold is varied through the microprocessor interface.

12. The receiver of claim 1 further comprising a synchronizer that synchronizes to a signal having an active interval the synchronizer comprising:

a first digital delay of period L;

a subtractor coupled to the input and output of the digital delay;

a unipolar output coupled to the output of the subtractor;

an adder/subtractor coupled to the unipolar output; and

a second digital delay of period M coupled to the adder/subtractor.

13. The receiver of claim 12 wherein the synchronizer further includes a RAM storing logarithm lookup tables, the lookup tables being addressed as a function of the output of the adder/subtractor.

14. The receiver of claim 1 further including a synchronizer that synchronizes to a signal having an active interval and a guard interval, the synchronizer comprising a digital delay having an input and an output defining a synchronizing interval, the synchronizer having an acquisition mode with a first synchronizing interval and a tracking mode with a second synchronizing interval, the first and second intervals being unequal.

15. The receiver of claim 14 wherein the FFT processor has an FFT window and the first synchronizing interval is equal to the FFT window.

16. The receiver of claim 15 wherein the second synchronizing interval is smaller that the FFT window.

17. The receiver of claim 14 wherein memory allocated to the FFT processor during FFT calculations is allocated to the synchronizer during synchronization.

18. The receiver of claim 14 wherein the synchronizer further comprises:

a correlator having an input coupled to the input and output of the digital delay and an output couple to a peak detector, the peak detector generating an output when the output of the correlator exceeds a threshold.

19. The receiver of claim 1 wherein the receiver has a synchronizer that detects boundaries of received symbols, the synchronizer comprising:

a threshold detector;

a statistical peak detector;

wherein the synchronizer'"'"'s choice between the threshold detector and the statistical peak detector is a function of the signal to noise ratio of the received signal.

20. The receiver of claim 1 wherein the FFT processor includes constant coefficient multipliers and multiplexers.

21. The receiver of claim 1 wherein the FFT processor performs a radix 2{circumflex over ( )}2+2 FFT.

22. The receiver of claim 1 wherein the FFT processor comprises:

RAM storing FFT coefficients; and

an address generator mapping addresses of redundant entries onto a single address.

23. The receiver of claim 22 wherein the FFT processor has a predefined breakpoint and the address generator maps an address above the breakpoint onto an address below the breakpoint.

24. The receiver of claim 23 wherein the FFT processor has a plurality of breakpoints, each breakpoint defining a change in an address increment for the FFT processor.

25. The receiver of claim 22 wherein the RAM stores a power of four table.

26. A receiver for receiving modulated symbols that have an active interval and a guard interval separated by a boundary, the receiver having a guard interval detector, said receiver comprising:

a measurement block;

a delay block having a delay approximately equal to the active interval;

a subtractor generating a difference sample corresponding to the difference in measured signal strength between a first symbol and a second delayed symbol;

a storage block storing N difference samples; and

a processing block applying a mathematical operation to the stored N difference samples.

27. The receiver of claim 26 wherein the processing block performs a statistical analysis.

28. The receiver of claim 26 wherein the delay block includes addressable RAM.

29. The receiver of claim 26 wherein the delay block includes a FIFO.

30. The receiver of claim 26 wherein the processing block includes a dispersion measurement.

31. The receiver of claim 26 wherein the guard interval detector measures a first dispersion over a first block of N difference samples and a second dispersion over a second block of N difference samples, the first and second block of difference samples being separated by at least one sample.

32. The receiver of claim 31 wherein the first and second blocks of difference samples are not contiguous.

33. The receiver of claim 31 wherein the guard interval detector generates a signal based on a statistical relationship between the two dispersion calculations, the statistical relationship having a known probability function.

34. The receiver of claim 33 wherein the probability function is an F ratio.

35. The receiver of claim 31 wherein the dispersion calculations are submitted to a peak detector having statistical tests of significance.

36. A method of processing a modulated multi-carrier signal, said method comprising the step of:

receiving digitized data representing modulated multi-carrier symbols having an active interval and a guard interval;

passing the received data through an I/Q demodulator;

synchronizing an FFT window to the active interval;

performing an FFT on the active interval;

estimating the channel characteristics; and

producing an output including unmodulated digitized video data corresponding to the received modulated multi-carrier signal, said steps of passing, synchronizing, performing, applying, estimating, and producing being performed within a single ship.

37. The method of claim 36 wherein the producing step results in an MPEG encoded output.

38. The method of claim 36 further comprising the steps of:

extracting pilot carriers from the received digitized data;

determining phase differences in the pilot carriers; and

applying feedback to the I/Q demodulation as a function of the determined phase differences in the pilot carriers.

39. A method for synchronizing an FFT window to a modulated multi-carrier signal having symbols, said method comprising the steps of:

choosing a pair of blocks of symbols;

measuring a characteristic of a first symbol of a first block of the pair;

measuring a characteristic of a first symbol of a second block of the pair;

determining the difference between the first symbol of the first block and the first symbol of the second block;

repeating the measuring steps and the determination step for successive symbols in each block; and

applying a statistical test to the determined differences between the first and second blocks.

40. The method of claim 39 wherein the statistical test is an F ratio test.

41. The method of claim 39 further comprising the steps of choosing a second pair of blocks, and performing said measuring, determining, repeating, and applying steps on the second pair.

42. A method for synchronizing an FFT window to a modulated multi-carrier signal having symbols, said method comprising the steps of:

receiving a digital signal corresponding to the multi-carrier signal;

producing a delayed signal by delaying the received signal by L symbols;

determining the difference between the delayed signal and the received signal and producing a difference signal;

delaying the difference signal by N symbols;

inputting the difference signal and the delayed difference signal into an adder/subtractor;

delaying the output of the adder/subtractor; and

feeding back the delayed output of the adder/subtractor as an additional input into the adder/subtractor.

43. A method for synchronizing an FFT window to a modulated multi-carrier signal having symbols, said method comprising the steps of:

receiving a digital signal corresponding to the multi-carrier signal;

delaying the digital signal producing a delayed signal;

correlating the delayed signal to the received signal; and

accessing data in a lookup table stored in memory as a function of the correlating.

44. A method for synchronizing an FFT window to a modulated multi-carrier signal having symbols, said method comprising the steps of:

receiving a digital signal corresponding to the multi-carrier signal;

measuring the signal to noise ratio of the digital signal; and

choosing a selected synchronization technique from a plurality of synchronization techniques, said choosing step performed as a function of the measure of signal to noise ratio.

45. The method of claim 44 wherein said plurality of synchronization techniques includes use of a threshold detector and alternatively use of a statistical peak detector.