Dual purpose serial/parallel data transfer device for peripheral storage device

• US 6,687,775 B1
• Filed: 11/28/2000
• Issued: 02/03/2004
• Est. Priority Date: 11/28/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bassett, Stephen J.
• Primary Examiner(s): Gaffin, Jeffrey
• Assistant Examiner(s): KNAPP, JUSTIN R
• Application Number:
  US09/724,365
• Time in Patent Office: 1,162 Days
• Field of Search: 710/8, 710/70-74, 710/62
• US Class Current: 710/70
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0676 Magnetic disk device

Abstract

A peripheral storage device system and a data transfer device for use in a peripheral storage device system are disclosed, which provide for selective information transfer between a peripheral storage device, such as a disk drive, a CDROM drive, or a tape drive, and a host computer in a serial or parallel data format. A cable connector and cable assembly are disclosed for connecting the peripheral storage device system with the host computer, whereby serial data transfer may be accomplished via an ATA connector on one or both of the peripheral storage device and the host computer. In addition, a methodology is disclosed for transferring data between a peripheral storage device and a host computer in one of a serial and a parallel data format.

Claims

1. In a peripheral storage device, a data transfer device for transferring information between the peripheral storage device and a host computer, comprising:

an output circuit operative to receive output information including first and second output data from the peripheral storage device and to selectively provide one of a single-ended output representative of the output information and a differential output representative of the output information to the host computer according to a first control signal; and

an input circuit operative to selectively receive one of a single-ended input and a differential input from the host computer according to the first control signal and to provide input information representative of the one of a single-ended input and a differential input to the peripheral storage device,

wherein the output circuit comprises first and second output buffers operative to receive the first and second output data, respectively, from the peripheral storage device and to provide first and second output signals representative of the first and second output data, respectively, according to the first control signal and wherein the input circuit comprises first and second input buffers operative to receive first and second input signals, respectively, and to selectively provide single-ended and differential input data representative of the first and second input signals, respectively, to the peripheral storage device according to the first control signal.

2. The data transfer device of claim 1, wherein the output circuit is operative to selectively provide one of a single-ended output representative of the first and second output data and a differential output representative of the first output data according to the first control signal.

3. The data transfer device of claim 2, wherein the input information comprises one of single-ended input data and differential input data, and wherein the input circuit is operative to selectively provide one of the single-ended input data representative of the single-ended input and the differential input data representative of the differential input according to the first control signal.

4. The data transfer device of claim 3, wherein the first control signal comprises one of a first control state and a second control state;

wherein the output circuit is operative to provide the single-ended output representative of the first and second output data if the first control signal is in the first control state, and to provide the differential output representative of the first output data if the first control signal is in the second control state; and

wherein the input circuit is operative to provide the single-ended input data representative of a single-ended input if the first control signal is in the first control state, and to provide the differential input data representative of a differential input if the first control signal is in the second control state.

5. The data transfer device of claim 4, wherein the first control signal is provided by a host interface operative to provide electrical communication between the data transfer device and the host computer.

6. The data transfer device of claim 1, wherein the input information comprises one of single-ended input data and differential input data, and wherein the input circuit is operative to selectively provide one of the single-ended input data representative of the single-ended input and the differential input data representative of the differential input according to the first control signal.

7. The data transfer device of claim 1, wherein the first output buffer is operative to provide a single-ended first output signal representative of the first output data if the first control signal is in the first control state, and a differential first output signal representative of the first output data when the first control signal is in the second control state, and wherein the second output buffer is operative to provide a single-ended second output signal representative of the second output data if the first control signal is in the first control state.

8. The data transfer device of claim 7, further comprising a host interface having first and second interface circuits operative to provide electrical communication between the data transfer device and the host computer, and wherein the output circuit comprises a first switching circuit operative according to the first control, signal to provide the single-ended first and second output signals to the first and second interface circuits, respectively, if the first control signal is in the first control state, and to provide the differential first output signal to the first and second interface circuits if the first control signal is in the second control state.

9. The data transfer device of claim 8, wherein the single-ended input comprises first and second single-ended inputs, wherein the first input buffer is operative to provide a first input data representative of the first single-ended input if the first control signal is in the first control state, and to provide the first input data representative of the differential input if the first control signal is in the second control state, and wherein the second input buffer is operative to provide a second input data representative of the second single-ended input if the first control signal is in the first control state.

10. The data transfer device of claim 9, wherein the input circuit comprises a second switching circuit operative according to the first control signal to provide the first and second single-ended inputs from the first and second interface circuits to the first and second input buffers, respectively, if the first control signal is in the first control state, and to provide the differential input from the first and second interface circuits to the first input buffer if the first control signal is in the second control state.

11. The data transfer device of claim 10, wherein the output circuit is operative to provide the first and second output signals if a second control signal is in an output state, and wherein the input circuit is operative to provide the first and second input data if the second control signal is in an input state.

12. The data transfer device of claim 10, wherein the first control signal is provided by the host interface.

13. The data transfer device of claim 1, wherein the single-ended input comprises first and second single-ended inputs, wherein the first input buffer is operative to provide a first input data representative of the first single-ended input if the first control signal is in the first control state, and to provide the first input data representative of the differential input if the first control signal is in the second control state, and wherein the second input buffer is operative to provide a second Input data representative of the second single-ended input if the first control signal is in the first control state.

14. The data transfer device of claim 13, further comprising a host interface having first and second interface circuits operative to provide electrical communication between the data transfer device and the host computer, and wherein the input circuit comprises a second switching circuit operative according to the first control signal to provide the first and second single-ended inputs from the first and second interface circuits to the first and second input buffers, respectively, if the first control signal is in the first control state, and to provide the differential input from the first and second interface circuits to the first input buffer if the first control signal is in the second control state.

15. The data transfer device of claim 1, wherein the peripheral storage device comprises one of a disk drive, a CDROM drive, and a tape drive.

16. A peripheral storage device system for providing information storage for a host computer, comprising:

a peripheral storage device operative to store information from the host computer;

a host interface operative to provide electrical communication between the peripheral storage device and the host computer; and

a data transfer device associated with the host interface and operative to selectively transfer information between the peripheral storage device and the host computer in one of a serial format and a parallel format,

wherein the data transfer device comprises;

an output circuit operative to receive output information including first and second output data from the peripheral storage device and to selectively provide one of a single-ended output representative of the output information and a differential output representative of the output information to the host computer according to a first control signal; and

an input circuit operative to selectively receive one of a single-ended input and a differential input from the host computer according to the first control signal and to provide input information representative of the one of a single-ended input and a differential input to the peripheral storage device,

wherein the output circuit comprises first and second output buffers operative to receive the first and second output data, respectively, from the peripheral storage device and to provide first and second output signals representative of the first and second output data, respectively, according to the first control signal and wherein the input circuit comprises first and second input buffers operative to receive first and second input signals, respectively, and to selectively provide single-ended and differential input data representative of the first and second input signals, respectively, to the peripheral storage device according to the first control signal.

17. The peripheral storage device system of claim 16, wherein the output circuit is operative to selectively provide one of a single-ended output representative of the first and second output data and a differential output representative of the first output data according to the first control signal.

18. The peripheral storage device system of claim 17, wherein the input information comprises one of single-ended Input data and differential input data, and wherein the input circuit is operative to selectively provide one of the single-ended input data representative of the single-ended input and the differential input data representative of the differential input according to the first control signal.

19. The peripheral storage device system of claim 18, wherein the first control signal comprises one of a first control state and a second control state;

wherein the output circuit is operative to provide the single-ended output representative of the first and second output data if the first control signal is in the first control state, and to provide the differential output representative of the first output data if the first control signal is in the second control state; and

wherein the input circuit is operative to provide the single-ended input data representative of a single-ended input if the first control signal is in the first control state, and to provide the differential input data representative of a differential input if the first control signal is in the second control state.

20. The peripheral storage device system of claim 19, wherein the first control signal is provided by the host interface.

21. The peripheral storage device system of claim 16, wherein the first output buffer is operative to provide a single-ended first output signal representative of the first output data if the first control signal is in the first control state, and a differential first output signal representative of the first output data when the first control signal is in the second control state, and wherein the second output buffer is operative to provide a single-ended second output signal representative of the second output data if the first control signal is in the first control state.

22. The peripheral storage device system of claim 21, wherein the host interface comprises first and second interface circuits operative to provide electrical communication between the data transfer device and the host computer, and wherein the output circuit comprises a first switching circuit operative according to the first control signal to provide the single-ended first and second output signals to the first and second interface circuits, respectively, if the first control signal is in the first control state, and to provide the differential first output signal to the first and second interface circuits if the first control signal is in the second control state.

23. The peripheral storage device system of claim 22, wherein the single-ended input comprises first and second single-ended inputs, wherein the first input buffer is operative to provide a first input data representative of the first single-ended input if the first control signal is in the first control state, and to provide the first input data representative of the differential input if the first control signal is in the second control state, and wherein the second input buffer is operative to provide a second input data representative of the second single-ended input if the first control signal is in the first control state.

24. The peripheral storage device system of claim 23, wherein the input circuit comprises a second switching circuit operative according to the first control signal to provide the first and second single-ended inputs from the first and second interface circuits to the first and second input buffers, respectively, if the first control signal is in the first control state, and to provide the differential input from the first and second interface circuits to the first input buffer if the first control signal is in the second control state.

25. The peripheral storage device system of claim 24, wherein the output circuit is operative to provide the first and second output signals if a second control signal is in an output state, and wherein the input circuit is operative to provide the first and second input data if the second control signal is in an input state.

26. The peripheral storage device system of claim 25, wherein the host interface comprises an ATA connector operative to provide electrical communication between the peripheral storage device system and the host computer in one of a serial format and a parallel format.

27. The peripheral storage device system of claim 16, wherein the host interface comprises an ATA connector operative to provide electrical communication between the peripheral storage device system and the host computer in one of a serial format and a parallel format.

28. The peripheral storage device system of claim 16, wherein the peripheral storage device comprises one of a disk drive, a CDROM drive, and a tape drive.