Arbitration system and method

• US 6,687,797 B1
• Filed: 05/17/2001
• Issued: 02/03/2004
• Est. Priority Date: 05/17/2001
• Status: Expired due to Term

• Current Assignee: Emc IP Holding Company LLC (Dell Technologies Inc.)
• Original Assignee: EMC Corporation (Dell Technologies Inc.)
• Inventors: Walton, John K.
• Primary Examiner(s): McLean-Mayo, Kimberly
• Application Number:
  US09/859,547
• Time in Patent Office: 992 Days
• Field of Search: 711/167, 711/112, 711/150, 711/151, 710/129, 710/131-132, 710/240, 710/241-244
• US Class Current: 711/150
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 3/0617 in relation to availability
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]

Abstract

An arbitration system having a common memory region. The region has a plurality of refreshable data storage elements. The system includes a plurality of memory region controllers each one being adapted to request access to the common memory region. Each one of the controllers has a memory refresh section for refreshing the data storage elements in the common memory. An arbitration unit is responsive to the requests from the plurality of memory region controllers, for granting access to the controllers in a sequence. The sequence comprises granting access to operative ones of the controllers sequentially with the refresh section of less than all of the access granted controllers being granted access to the common memory region during in the sequence.

Claims

1. A system comprising:

a common memory region having a plurality of refreshable data storage elements;

a plurality of memory region controllers each one being adapted to request access to the common memory region, each one of such controllers having a memory refresh section for refreshing the data storage elements in the common memory;

an arbitration unit responsive to the requests from the plurality of memory region controllers, for granting access to the controllers in a refresh sequence, such sequence comprising granting access to ones of the controllers determined to be operative in providing refresh to the data storage elements with controllers determined to be inoperative in providing refresh to the data storage elements being prevented from being granted access to the common memory region during the refresh sequence.

2. A system, comprising:

a common memory region having a plurality of refreshable data storage elements;

a plurality of memory region controllers each one being adapted to request access to the common memory region and to one of a pair of ports of such one of the controllers, each one of such controllers having a memory refresh section for refreshing the data storage elements in the common memory;

an arbitration unit responsive to the requests from the plurality of memory region controllers, for granting access to the controllers in a refresh sequence, such sequence comprising granting access to ones of the controllers determined to be operative in providing refresh to the data storage elements with both ports of each to the operative controllers being granted access to the common memory region and with the refresh section of ones of the controllers being determined to be inoperative in providing refresh to the data storage elements being prevented from being granted access to the common memory region during the refresh sequence.

3. A method for granting access to a common memory region system, comprising:

providing a pair of logic sections, each one of such logic sections having;

a port A controller, a port B controller; and

a memory refresh section;

granting access to the common memory array region based on the following round-robin arbitration;

a Condition I wherein;

If both the logic sections are operating properly, the memory refresh controller of a first one of the logic sections is used exclusively for memory refresh during the round-robin arbitration in accordance with the following sequential states;

State 1—

The port A controller of a first one of the logic sections is granted access to the memory region;

State 2—

The memory refresh section of the first one of the logic sections is granted access to the memory region;

State 3—

The port B controller of the first one of the logic sections is granted access to the memory region;

State 4—

The memory refresh section of the first one of the logic sections is granted access to the memory region;

State 5—

A check is made as to whether the second one of the logic sections requests access to the memory region and if such a request is made;

(a) The port A controllers of the second one of the logic sections is granted access to the memory region if such access is requested;

(b) The port B controllers of the second one of the logic sections is granted access to the memory region if Such access is requested;

State 6—

The process returns to State 1.

4. The method recited in claim 3 including a Condition II wherein:

If the second one of the logic sections is disabled, the second one of the logic sections is removed from the round-robin arbitration and memory refresh is provided exclusively by the first one of the logic sections memory refresh controller in accordance with the following sequential states;

State 1—

The port A controller of the first one of the logic sections is granted access to the memory region;

State 2—

The memory refresh section of the first one of the logic sections is granted access to the memory region;

State 3—

The port B controller of the first one of the logic sections is granted access to the memory region;

State 4—

The memory refresh section of the first one of the logic sections is granted access to the memory region;

State 5—

The process returns to State 1 of Condition II.

5. The method recited in claim 3 including a Condition III wherein if the first one of the logic sections is disabled such first one of the logic sections is removed from the round-robin arbitration with the memory refresh section of the second one of the logic sections performing memory refresh exclusively, such second one of the logic sections being is granted access to the memory region all the time in accordance with the following sequence:

State 1—

The port A controller of the second one of the logic sections is granted access to the memory region;

State 2—

The memory refresh section of the second one of the logic sections is granted access to the memory region;

State 3—

The port B controller of the second one of the logic sections is granted access to the memory region;

State 4—

The memory refresh section of the second one of the logic sections is granted access to the memory region; and

State 5—

The process returns to State 1 of Condition III.