Etch stop layer system

• US 6,689,211 B1
• Filed: 06/22/2000
• Issued: 02/10/2004
• Est. Priority Date: 04/09/1999
• Status: Active Grant

• Current Assignee: Charles Stark Draper Laboratory Incorporated
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Borenstein, Jeffrey T., Wu, Kenneth C., Taraschi, Gianna, Fitzgerald, Eugene A.
• Primary Examiner(s): KUNEMUND, ROBERT M
• Application Number:
  US09/599,260
• Time in Patent Office: 1,328 Days
• Field of Search: 117/94, 117/95, 117/97, 117/915, 117/939
• US Class Current: 117/94
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/76256 using silicon etch back techniques, e.g. BESOI, ELTRAN
• CPC Class Codes: Y10S 117/915 Separating from substrate

Abstract

A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si_1−xGe_x alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×10¹⁹ cm⁻³ of boron or undoped Si_1−xGe_x alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium. Furthermore, the nondegenerate doping in the Si_1−xGe_x alloy should not affect the etch-stop behavior. The etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material. Nominally, the buffer has a linearly-changing composition with respect to thickness, from pure silicon at the substrate/buffer interface to a composition of germanium, and dopant if also present, at the buffer/etch-stop interface which can still be etched at an appreciable rate. Here, there is a strategic jump in germanium and concentration from the buffer side of the interface to the etch-stop material, such that the etch-stop layer is considerably more resistant to the etchant. This process and layer structure allows for an entire range of new materials for microelectronics. The etch-stop capabilities introduce new novel processes and structures such as relaxed SiGe alloys on Si, SiO₂, and SiO₂/Si. Such materials are useful for future strained Si MOSFET devices and circuits.

Claims

1. A monocrystalline etch-stop layer system for use on a monocrystalline Si substrate, said system comprising a substantially relaxed graded layer of Si₁₋

xGe_x, and a uniform etch-stop layer of substantially relaxed Si<sub>1−

y</sub>Ge_y, wherein said uniform etch-stop layer of Si<sub>1−

y</sub>Ge_y has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

2. The system of claim 1, wherein x<

0.20.

3. The system of claim 1, wherein y>

0.19.

4. The system of claim 1, wherein x<

0.20 and y>

0.19.

5. The system of claim 1, wherein said Si₁₋

yGe_y layer is bonded to a second substrate.

6. The system of claim 5, wherein said second substrate comprises Si.

7. The system of claim 5, wherein said second substrate comprises glass.

8. The system of claim 5, wherein said second substrate comprises quartz.

9. The system of claim 5, wherein said second substrate comprises a layer of SiO₂ on a second Si substrate.

10. The system of claim 5, wherein the first Si substrate and graded layer are substantially removed.

11. The system of claim 6, wherein the first Si substrate and graded layer are substantially removed.

12. The system of claim 7, wherein the first Si substrate and graded layer are substantially removed.

13. The system of claim 8, wherein the first Si substrate and graded layer are substantially removed.

14. The system of claim 9, wherein the first Si substrate and graded layer are substantially removed.

15. The system of claim 1, wherein a SiO₂ layer is deposited onto said Si₁₋

yGe_y layer.

16. The system of claim 15, wherein said SiO₂ layer is bonded to a second substrate.

17. The system of claim 16, wherein said second substrate comprises a layer of SiO₂ on a second Si substrate.

18. The system of claim 16, wherein said second substrate comprises a layer of SiO₂ on a glass substrate.

19. The system of claim 16, wherein said second substrate comprises a layer of SiO₂ on a quartz substrate.

20. The system of claim 16, wherein the first Si substrate and graded layer are substantially removed.

21. The system of claim 17, wherein the first Si substrate and graded layer are substantially removed.

22. The system of claim 18, wherein the first Si substrate and graded layer are substantially removed.

23. The system of claim 19, wherein the first Si substrate and graded layer are substantially removed.

24. The system of claim 10, wherein the surface is planarized.

25. The system of claim 11, wherein the surface is planarized.

26. The system of claim 12, wherein the surface is planarized.

27. The system of claim 13, wherein the surface is planarized.

28. The system of claim 14, wherein the surface is planarized.

29. The system of claim 20, wherein the surface is planarized.

30. The system of claim 21, wherein the surface is planarized.

31. The system of claim 22, wherein the surface is planarized.

32. The system of claim 23, wherein the surface is planarized.

33. A monocrystalline etch-stop layer system for use on a monocrystalline Si substrate, said system comprising a substantially relaxed graded layer of Si₁₋

xGe_x;

a uniform etch-stop layer of substantially relaxed Si<sub>1−

y</sub>Ge_y; and

a strained Si<sub>1−

z</sub>Ge_z layer, wherein said uniform etch-stop layer of Si<sub>1−

y</sub>Ge_y has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

34. The system of claim 33, wherein z<

y.

35. The system of claim 33, wherein y>

0.18.

36. The system of claim 33, wherein y>

0.18 and z<

y.

37. The system of claim 33, wherein y>

0.18 and z=0.

38. The system of claim 33, wherein said Si₁₋

zGe_z is bonded to a second substrate.

39. The system of claim 38, wherein said second substrate comprises Si.

40. The system of claim 38, wherein said second substrate comprises glass.

41. The system of claim 38, wherein said second substrate comprises quartz.

42. The system of claim 38, wherein said second substrate comprises a layer of SiO₂ on a second Si substrate.

43. The system of claim 38, wherein the first Si substrate and graded layer are substantially removed.

44. The system of claim 39, wherein the first Si substrate and graded layer are substantially removed.

45. The system of claim 40, wherein the first Si substrate and graded layer are substantially removed.

46. The system of claim 41, wherein the first Si substrate and graded layer are substantially removed.

47. The system of claim 42, wherein the first Si substrate and graded layer are substantially removed.

48. The structure in claim 33 in which a SiO₂ layer is deposited onto said Si₁₋

zGe_z layer.

49. The system of claim 48, wherein said SiO₂ layer is bonded to a second substrate.

50. The system of claim 49, wherein the second substrate comprises a layer of SiO₂ on a second Si substrate.

51. The system of claim 49, wherein the second substrate comprises a layer of SiO₂ on a glass substrate.

52. The system of claim 49, wherein the second substrate comprises a layer of SiO₂ on a quartz substrate.

53. The system of claim 49, wherein the first Si substrate and graded layer are substantially removed.

54. The system of claim 50, wherein the first Si substrate and graded layer are substantially removed.

55. The system of claim 51, wherein the first Si substrate and graded layer are substantially removed.

56. The system of claim 52, wherein the first Si substrate and graded layer are substantially removed.

57. A monocrystalline etch-stop layer system for use on a monocrystalline Si substrate, comprising a substantially relaxed graded layer of Si₁₋

xGe_x;

a uniform etch-stop layer of substantially relaxed Si<sub>1−

y</sub>Ge_y;

a second etch-stop layer of strained Si<sub>1−

z</sub>Ge_z; and

a substantially relaxed Si<sub>1−

w</sub>Ge_w layer, wherein said uniform etch-stop layer of Si<sub>1−

y</sub>Ge_y has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

58. The system of claim 57, wherein y−

0.05<

w<

y+0.05.

59. The system of claim 57, wherein w=y.

60. The system of claim 57, wherein said Si₁₋

wGe_w is bonded to a second substrate.

61. The system of claim 60, wherein said second substrate comprises Si.

62. The system of claim 60, wherein said second substrate comprises glass.

63. The system of claim 60, wherein said second substrate comprises quartz.

64. The system of claim 60, wherein said second substrate comprises a layer of SiO₂ on a second Si substrate.

65. The system of claim 60, wherein the first Si substrate and graded layer are substantially removed.

66. The system of claim 61, wherein the first Si substrate and graded layer are substantially removed.

67. The system of claim 62, wherein the first Si substrate and graded layer are substantially removed.

68. The system of claim 63, wherein the first Si substrate and graded layer are substantially removed.

69. The system of claim 64, wherein the first Si substrate and graded layer are substantially removed.

70. The system of claim 57, wherein a SiO₂ layer is deposited onto said Si₁₋

wGe_w layer.

71. The system of claim 70, wherein said SiO₂ layer is bonded to a second substrate.

72. The system of claim 70, wherein the second substrate comprises a layer of SiO₂ on a second Si substrate.

73. The system of claim 70, wherein the second substrate comprises a layer of SiO₂ on a glass substrate.

74. The system of claim 70, wherein the second substrate comprises a layer of SiO₂ on a quartz substrate.

75. The system of claim 70, wherein the first Si substrate and graded layer are substantially removed.

76. The system of claim 71, wherein the first Si substrate and graded layer are substantially removed.

77. The system of claim 72, wherein the first Si substrate and graded layer are substantially removed.

78. The system of claim 73, wherein the first Si substrate and graded layer are substantially removed.

79. The system of claim 74, wherein the first Si substrate and graded layer are substantially removed.

80. A method of integrating a device or layer comprising:

depositing a substantially relaxed graded layer of Si<sub>1−

x</sub>Ge_x on a Si substrate;

depositing a uniform etch-stop layer of substantially relaxed Si<sub>1−

y</sub>Ge_y on said graded buffer; and

etching portions of said substrate and said graded buffer in order to release said etch-stop layer, wherein

said uniform etch-stop layer of Si<sub>1−

y</sub>Ge_y has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

81. The method of claim 80, wherein x<

0.20.

82. The method of claim 80, wherein y>

0.19.

83. The method of claim 80, wherein x<

0.20 and y>

0.19.

84. The method of claim 80, wherein the etchant used to release the etch-stop layer is KOH.

85. The method of claim 80, wherein the etchant used to release the etch-stop layer is TMAH.

86. The method of claim 80, wherein the etchant used to release the etch-stop layer is EDP.

87. The method of claim 80, wherein the etch-stop is released and the etch-stop layer is planarized.

88. The method of claim 87, wherein the method of planarization is chemical-mechanical polishing (CMP).

89. A method of integrating a device or layer comprising:

depositing a substantially relaxed graded layer of Si<sub>1−

x</sub>Ge_x on a Si substrate;

depositing a uniform first etch-stop layer of substantially relaxed Si<sub>1−

y</sub>Ge_y on said graded buffer;

depositing a second etch-stop layer of strained Si<sub>1−

z</sub>Ge_z;

depositing a substantially relaxed Si<sub>1−

w</sub>Ge_w layer;

etching portions of said substrate and said graded buffer in order to release said first etch-stop layer, and

etching portions of said residual graded buffer in order to release the second etch-stop Si<sub>1−

z</sub>Ge_z layer, wherein

said uniform etch-stop layer of Si<sub>1−

y</sub>Ge_y has a relative etch rate which is less than approximately the relative etch rate of Si doped with 7×

10¹⁹ boron atoms/cm³.

90. The method of claim 89, wherein the etchant used to release the second etch-stop layer comprises an oxidant and an oxide stripping agent.

91. The method of claim 90, wherein the oxidant oxidizes Ge much more rapidly than Si.

92. The method of claim 90, wherein the oxidant comprises H₂O₂.

93. The method of claim 90, wherein the stripping agent comprises HF.

94. The method of claim 90, wherein the oxidant comprises H₂O₂ and the stripping agent comprises HF.

95. The method of claim 94, wherein the diluting agent comprises CH₃COOH.

96. The method of claim 95, wherein the ratio of chemicals in the etchant are (1:

2;

3) for (HF;

H₂O₂;

CH₃COOH).

97. The method of claim 89, wherein wet oxidation is used to selectively oxidize the Si₁₋

xGe_x and Si<sub>1−

y</sub>Ge_y, thereby acting as an etch-stop with respect to Si<sub>1−

z</sub>Ge_z.

98. The method of claim 97, wherein the wet oxidation temperature is <

750 degrees Celsius.

99. The method of claim 97, wherein the oxidized layers are removed by an HF and water solution.

100. The method of claim 98, wherein the oxidized layers are removed by an HF solution.

101. The method of claim 90, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

102. The method of claim 91, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

103. The method of claim 92, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

104. The method of claim 93, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

105. The method of claim 94, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

106. The method of claim 95, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

107. The method of claim 96, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

108. The method of claim 97, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

109. The method of claim 98, Wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

110. The method of claim 99, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.

111. The method of claim 100, wherein the Si₁₋

zGe_z layer is subsequently removed using a selective etchant with respect to the Si<sub>1−

w</sub>Ge_w layer.