Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

• US 6,689,644 B2
• Filed: 04/22/2002
• Issued: 02/10/2004
• Est. Priority Date: 08/13/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Johnson, Mark G.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Vu, David
• Application Number:
  US10/128,188
• Publication Number:
  US 20030064572A1
• Time in Patent Office: 659 Days
• Field of Search: 438/128-132, 438/197, 438/210, 438/600-601
• US Class Current: 438/131
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Claims

1. A process for fabricating a memory array comprising:

(a) forming a first layer of conductive material;

(b) forming a set of second layers for defining memory elements on the first layer;

(c) patterning the set of second layers into a plurality of parallel, spaced-apart strips;

(d) etching the first layer in alignment with the strips formed from the set of second layers;

(e) forming a third layer of conductive material on the strips formed from the set of second layers;

(f) forming a set of fourth layers for defining memory elements of the second level;

(g) patterning the set of fourth layers into a plurality of parallel, spaced-apart strips, the strips formed from the set of fourth layers running generally perpendicular to the strips formed from the first layer;

(h) etching the third layer and the strips formed from the set of second layers in alignment with the strips formed from the set of fourth layers;

said set of second layers comprising a first anti-fuse layer, said set of fourth layers comprising a second anti-fuse layer, said anti-fuse layers each positioned between a respective pair of diode components that form a diode only after the respective anti-fuse layer is disrupted.

2. The process defined by claim 1 including:

forming a fifth layer of conductive material on the strips formed from the set of fourth layers;

patterning the fifth layer into a plurality of parallel, spaced-apart conductors running generally perpendicular to the strips in the set of fourth layers; and

etching the strips formed from the set of fourth layers in alignment with the conductors, thereby defining additional memory cells.

3. The process defined by claim 1 repeating (a) through (h).

4. The process defined by claim 3 in combination with the acts of claim 2.

5. The process defined by claim 1 repeating the steps (a) through (h) a plurality of times.

6. The process defined by claim 5 in combination with the acts of claim 2.

7. The process defined by claim 1 including depositing an insulator and etching it back to planarize the structure and opening electrical contacts to the strips formed from the set of second layers between (d) and (e).

8. The process defined by claim 1 wherein the set of second layers and set of fourth layers each comprise layers of polysilicon and silicon dioxide.

9. The process defined by claim 1 wherein the set of second layers and set of fourth layers each comprise layers of polysilicon and silicon oxynitride.

10. The process defined by claim 1 wherein the anti-fuse layers comprise silicon dioxide.

11. The process defined by claim 1 wherein the anti-fuse layers comprise silicon oxynitride.

12. The process defined by claim 1 wherein a planarization step occurs after the forming of the set of second layers and before the forming of the third layer.

13. The process defined by claim 12 wherein the planarization is performed by chemical-mechanical polishing.

14. The process defined by claim 8 wherein the polysilicon is deposited at low temperature using chemical vapor deposition.

15. The process defined by claim 1 including the use of ion implanted silicon.

16. The process defined by claim 1 including the use of in-situ doped silicon.

17. The process defined by claim 16 wherein the silicon is deposited using LPCVD.

18. The process defined by claim 16 wherein the silicon is deposited using PECVD.

19. The process defined by claim 16 wherein the silicon is deposited using PVD.

20. The process defined by claim 16 wherein the silicon is deposited using UHVCVD.