MOS Semiconductor device

• US 6,690,061 B2
• Filed: 09/25/2002
• Issued: 02/10/2004
• Est. Priority Date: 09/26/2001
• Status: Expired

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tanaka, Bungo, Yoneda, Tatsuo
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/253,522
• Publication Number:
  US 20030057503A1
• Time in Patent Office: 503 Days
• Field of Search: 257/330-332
• US Class Current: 257/331
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49111 the connectors connecting two common bonding areas, e.g. Litz or braid wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

The semiconductor device according to an aspect of the present invention includes: a semiconductor substrate of a first conductive type; a first semiconductor layer of the first conductive type formed on the main surface of the semiconductor substrate, the impurity concentration of the first semiconductor layer being lower than that of the semiconductor substrate; a second and third semiconductor layers of a second conductive type formed on the first semiconductor layer, the second and third semiconductor layers being isolated from each other; a first and second MOS transistors MOS1 and MOS2 of the first conductive type formed in the second and third semiconductor layers, the first semiconductor layer and the semiconductor substrate serving as drains of the first and second MOS transistors; and a conductive layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of a first conductive type;

a first semiconductor layer of the first conductive type formed on a main surface of said semiconductor substrate, an impurity concentration of said first semiconductor layer being lower than that of said semiconductor substrate;

second and third semiconductor layers of a second conductive type formed on said first semiconductor layer

a first MOS transistor of the first conductive type including first source regions formed in said second semiconductor layer, said first semiconductor layer and said semiconductor substrate serving as drains of said first MOS transistor;

a first metal layer electrically connected to said first source regions

a second MOS transistor of the first conductive type including second source regions;

formed in said third semiconductor layer, said first semiconductor layer and said semiconductor substrate serving as drains of said second MOS transistor;

a second metal layer electrically connected to said second source regions, said second metal layer being isolated from said first metal layer; and

a conductive layer formed on a reverse surface of said semiconductor substrate.

2. The semiconductor device according to claim 1, wherein:

said first MOS transistor includes a gate electrode formed, via a gate insulating film, in a trench formed in said second semiconductor layer so as to reach said first semiconductor layer, and said first source regions provided near a surface of said second semiconductor layer at both sides of said trench, said first source regions contacting said trench; and

said second MOS transistor includes a gate electrode formed, via a gate insulating film, in a trench formed in said third semiconductor layer so as to reach said first semiconductor layer, and said second source regions provided near a surface of said third semiconductor layer at both sides of said trench, said second source regions contacting said trench.

3. The semiconductor device according to claim 2, wherein:

each of said first and second MOS transistors includes a plurality of said gate electrodes and a respective plurality of said first and second source regions;

said first and second source regions of said first and second MOS transistors are covered by respective first and second metal layers; and

solder balls for drawing source electrodes are formed on the common metal layers.

4. The semiconductor device according to claim 3, wherein said gate electrodes of each of said first and second MOS transistors are commonly connected.

5. The semiconductor device according to claim 3, further comprising:

a fourth semiconductor layer of the second conductive type, provided near a surface of said second semiconductor layer between adjacent gate electrodes of said first MOS transistor and between said first source regions corresponding to the adjacent gate electrodes, an impurity concentration of said fourth semiconductor layer being higher than that of said second semiconductor layer; and

a fifth semiconductor layer of the second conductive type, provided near a surface of said third semiconductor layer between adjacent gate electrodes of said second MOS transistor and between said second source regions corresponding to the adjacent gate electrodes, impurity concentration of said fifth semiconductor layer being higher than that of said third semiconductor layer.

6. The semiconductor device according to claim 5, wherein said fourth and fifth semiconductor layers are covered by said respective first and second metal layers.

7. The semiconductor device according to claim 1, wherein said first semiconductor layer is an epitaxial layer.

8. The semiconductor device according to claim 1, wherein said conductive layer is formed of a vanadium-nickel-gold alloy or aluminum.

9. The semiconductor device according to claim 2, wherein the gate electrode of the first MOS transistor is electrically isolated from the gate electrode of the second MOS transistor.