×

Transistor configuration with a shielding electrode outside an active cell array and a reduced gate-drain capacitance

  • US 6,690,062 B2
  • Filed: 03/19/2003
  • Issued: 02/10/2004
  • Est. Priority Date: 03/19/2002
  • Status: Expired due to Term
First Claim
Patent Images

1. A transistor configuration, comprising:

  • a substrate;

    at least one active cell array including at least one transistor cell configured in said substrate;

    an edge region surrounding at least sections of said active cell array;

    an insulator layer;

    a drain zone configured in said substrate; and

    at least one shielding electrode;

    said substrate having a substrate surface and a substrate rear side located opposite said substrate surface;

    said transistor cell having a gate electrode electrically insulated from said substrate by said insulator layer;

    said edge region having an electrically conductive edge gate structure connected to said gate electrode; and

    at least sections of said shielding electrode configured between said edge gate structure and said drain zone.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×