Transistor configuration with a shielding electrode outside an active cell array and a reduced gate-drain capacitance

• US 6,690,062 B2
• Filed: 03/19/2003
• Issued: 02/10/2004
• Est. Priority Date: 03/19/2002
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hirler, Franz, Rieger, Walter, Poelzl, Martin, Krumrey, Joachim, Henninger, Ralf
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US10/391,997
• Publication Number:
  US 20030178676A1
• Time in Patent Office: 328 Days
• Field of Search: 257/340, 257/341, 257/386, 257/488, 257/630, 257/659
• US Class Current: 257/340
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The switching behavior of a transistor configuration is improved by providing a shielding electrode in an edge region. The shielding electrode surrounds at least sections of an active cell array. The capacitance between an edge gate structure and a drain zone and hence the gate-drain capacitance CGD of the transistor configuration is reduced by the shielding electrode located in the edge region.

Claims

1. A transistor configuration, comprising:

a substrate;

at least one active cell array including at least one transistor cell configured in said substrate;

an edge region surrounding at least sections of said active cell array;

an insulator layer;

a drain zone configured in said substrate; and

at least one shielding electrode;

said substrate having a substrate surface and a substrate rear side located opposite said substrate surface;

said transistor cell having a gate electrode electrically insulated from said substrate by said insulator layer;

said edge region having an electrically conductive edge gate structure connected to said gate electrode; and

at least sections of said shielding electrode configured between said edge gate structure and said drain zone.

2. The transistor configuration according to claim 1, further comprising:

a trench formed in said substrate;

said transistor cell configured along said trench; and

said gate electrode configured in said trench.

3. The transistor configuration according to claim 1, further comprising:

a trench formed in said substrate;

a further insulator layer; and

a field electrode oriented toward said substrate rear side;

said field electrode configured in said trench and below said gate electrode; and

said field electrode electrically insulated from said gate electrode and from said substrate by said insulator layer and said further insulator layer.

4. The transistor configuration according claim 1, wherein said active cell array includes a plurality of transistor cells.

5. The transistor configuration according claim 4, wherein said plurality of transistor cells are configured in strip form.

6. The transistor configuration according to claim 4, wherein said plurality of transistor cells are configured in strip form and in parallel one beside another.

7. The transistor configuration according to claim 1, further comprising:

a trench formed in said substrate;

a further insulator layer; and

a field electrode oriented toward said substrate rear side;

said field electrode configured in said trench and below said gate electrode;

said field electrode electrically insulated from said gate electrode and from said substrate by said insulator layer and said further insulator layer;

said shielding electrode electrically conductively connected to said field electrode.

8. The transistor configuration according to claim 1, further comprising a source metallization electrically conductively connected to said shielding electrode.

9. The transistor configuration according to claim 1, further comprising:

a control device electrically conductively connected to said shielding electrode;

said control device for controlling a potential on said shielding electrode for counteracting a crosstalk of signals between said edge gate structure and said drain zone.

10. The transistor configuration according to claim 1, wherein said edge gate structure is embodied as a gate ring made of polysilicon that at least partly encloses said active cell array.

11. The transistor configuration according to claim 1, further comprising:

a plurality of insulator layers;

said shielding electrode configured as a planar layer made of doped polysilicon located between said substrate surface and said edge gate structure; and

said plurality of insulator layers electrically insulating said shielding electrode from said substrate surface and said edge gate structure.

12. The transistor configuration according to claim 1, further comprising:

a well formed in said substrate below said edge gate structure;

said shielding electrode being formed by said well;

said edge region being a part of said substrate having a doping of a first conductivity type; and

said well having a doping of a conductivity type opposite the first conductivity type.

13. The transistor configuration according to claim 1, further comprising:

a further insulator layer having a large layer thickness configured between said edge gate structure and said shielding electrode; and

said further insulator layer minimizing a capacitance between said edge gate structure and said shielding electrode.

14. The transistor configuration according to claim 1, further comprising:

a first metallization plane having a source metallization and a gate metallization; and

a second metallization plane located between said substrate surface and said first metallization plane;

said edge gate structure including a material of a high conductivity in said second metallization plane.

15. The transistor configuration according to claim 1, further comprising a gate metallization forming said edge gate structure.

16. The transistor configuration according to claim 1, wherein said edge gate structure includes aluminum.

17. The transistor configuration according to claim 1, further comprising:

a conductive drain-up structure configured in said substrate; and

a metallization configured above said substrate surface;

said conductive drain-up structure being electrically insulated from said substrate;

said conductive drain-up structure electrically conductively connecting said drain zone to said metallization configured above said substrate surface.

18. The transistor configuration according to claim 1, further comprising:

a drain metallization adjoining said drain zone;

said drain zone being electrically conductively connected to said drain metallization.

19. The transistor configuration according to claim 1, further comprising:

a plurality of adjacent transistor cells having a plurality of trenches and a plurality of gate electrodes;

a plurality of transverse trenches configured between said plurality of trenches of said plurality of adjacent transistors cells;

said plurality of transverse trenches electrically conductively connecting said plurality of said gate electrodes of said plurality of adjacent transistors cells.

20. The transistor configuration according to claim 1, further comprising:

a plurality of adjacent transistor cells having a plurality of trenches and a plurality of field electrodes;

a plurality of transverse trenches configured between said plurality of trenches of said plurality of adjacent transistors cells;

said plurality of transverse trenches electrically conductively connecting said plurality of said field electrodes of said plurality of adjacent transistors cells.