LDO voltage regulator having efficient current frequency compensation

• US 6,690,147 B2
• Filed: 05/23/2002
• Issued: 02/10/2004
• Est. Priority Date: 05/23/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bonto, Olivier
• Primary Examiner(s): STERRETT, JEFFREY L
• Application Number:
  US10/153,938
• Publication Number:
  US 20030218450A1
• Time in Patent Office: 628 Days
• Field of Search: 323/273, 323/280
• US Class Current: 323/280
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

A low drop out linear voltage regulator (200) overcomes the dynamic quiescent current limitation by creating an internal zero that moves in the same direction and has the same amplitude as that of the output pole without sensing a portion of the load current. The low drop out linear voltage regulator (200) having frequency compensation in accordance with the present invention includes an error amplifier (202), a NMOS pass transistor (204), a variable compensation network (C_i, 206), and a stabilization circuit (208, 210, I₃, I₄). The error amplifier (202) includes a power supply input connected to a first power supply, a non-inverting input coupled to a reference voltage, a inverting input and an output terminal. The NMOS pass transistor (204) includes a source connected to an output terminal of the voltage regulator, a drain coupled to the second power supply, and a gate coupled to the output terminal of the error amplifier. The variable compensation network (C_i, 206) connects to the error amplifier. More particularly, the variable compensation network may include an RC circuit comprising a resistive transistor (206) and a capacitance (C_i) coupled in series. The stabilization circuit (208, 210, I₃, I₄) couples between the NMOS pass transistor (204) and the resistive transistor (206), such that the ratio of the impedance of the NMOS pass transistor (204) to the impedance of the resistive transistor (206) is constant.

Claims

1. A low drop out linear voltage regulator having frequency compensation, a first and a second power supply, comprising:

an error amplifier having a control input coupled to the first power supply, a non-inverting input coupled to a reference voltage, an inverting input and an output terminal;

an NMOS pass transistor having a source connected to an output terminal of the voltage regulator, a drain coupled to the second power supply, and a gate coupled to the output terminal of the error amplifier;

a variable compensation network connected to the output terminal of the error amplifier, wherein the variable compensation network includes an RC circuit comprising a resistive transistor and a capacitance coupled in series; and

a stabilization circuit coupled between the NMOS pass transistor and the resistive transistor, to equalize the gate to source voltage of the NMOS pass transistor and the gate to source voltage of the resistive transistor, wherein the stabilization circuit comprises,

a first bias current source coupled between the gate of the resistive transistor and ground,

a second bias current source coupled between the source of the resistive transistor and ground,

a first bias transistor having a source coupled to the gate of the resistive transistor, a drain coupled to the first power supply, a gate coupled to the gate of the NMOS pass transistor, and

a second bias transistor having a source coupled to the second bias current source, a gate coupled to the output terminal of the voltage regulator, a drain coupled to the first power supply.

2. A voltage regulator as recited in claim 1, further comprising a voltage divider connected between the output terminal of the voltage regulator and the inverting input of the error amplifier, the voltage divider coupled in a feedback loop to the inverting input of the error amplifier.

3. A voltage regulator as recited in claim 1, wherein the NMOS pass transistor is a NMOS power transistor having an extended drain.

4. A voltage regulator as recited in claim 1, wherein the resistive transistor is a NMOS power transistor having an extended drain.

5. A voltage regulator as recited in claim 1, wherein the second bias transistor is a NMOS power transistor having an extended drain.

6. A voltage regulator as recited in claim 1, wherein the first bias transistor is a NMOS power transistor having an extended drain.