Correction of duty-cycle distortion in communications and other circuits
First Claim
1. A circuit comprising:
- first and second supply nodes having first and second voltage levels, respectively;
an amplifier having first and second differential outputs for providing a clock signal;
a digital circuit having first and second differential inputs;
a first capacitor having first and second nodes, with the first node coupled to the first output of the amplifier and the second node coupled to the first input of the digital circuit;
a second capacitor having first and second nodes, with the first node coupled to the second output of the amplifier and the second node coupled to the second input of the digital circuit;
first and second subcircuits for setting a DC voltage at the first input of the digital circuit to a third voltage level that is between the first and second voltage levels;
wherein the first subcircuit is coupled between the second node of the first capacitor and the first supply node; and
wherein the second subcircuit is coupled between the second node of the first capacitor and the second supply node; and
third and fourth subcircuits for setting a DC voltage at the second input of the digital circuit to a fourth voltage level that is between the first and second voltage levels;
wherein the third subcircuit is coupled between the second node of the second capacitor and the first supply node; and
wherein the fourth subcircuit is coupled between the second node of the second capacitor and the second supply node.
1 Assignment
0 Petitions
Accused Products
Abstract
In some communications circuits a phenomenon called duty-cycle distortion—that is, a distortion of the apparent duration of the pulses in clock signals—causes the circuits to read clock signals as having a different duration than intended. Accordingly, the inventors devised unique circuitry for correcting or preventing this distortion. One exemplary circuit uses a voltage divider, comprising a pair of transistors, to set the DC or average voltage of the clock signals input to the digital circuit at a level approximating the logic threshold voltage of the digital circuit. In another example, a feedback circuit drives the DC or average voltage of signals input to the digital circuit to match a reference voltage that is substantially equal to the logic threshold voltage. In both examples, equating the DC or average voltage of the clock signals to the logic threshold voltage of the digital circuit reduces or prevents duty-cycle distortion.
27 Citations
10 Claims
-
1. A circuit comprising:
-
first and second supply nodes having first and second voltage levels, respectively;
an amplifier having first and second differential outputs for providing a clock signal;
a digital circuit having first and second differential inputs;
a first capacitor having first and second nodes, with the first node coupled to the first output of the amplifier and the second node coupled to the first input of the digital circuit;
a second capacitor having first and second nodes, with the first node coupled to the second output of the amplifier and the second node coupled to the second input of the digital circuit;
first and second subcircuits for setting a DC voltage at the first input of the digital circuit to a third voltage level that is between the first and second voltage levels;
wherein the first subcircuit is coupled between the second node of the first capacitor and the first supply node; and
wherein the second subcircuit is coupled between the second node of the first capacitor and the second supply node; and
third and fourth subcircuits for setting a DC voltage at the second input of the digital circuit to a fourth voltage level that is between the first and second voltage levels;
wherein the third subcircuit is coupled between the second node of the second capacitor and the first supply node; and
wherein the fourth subcircuit is coupled between the second node of the second capacitor and the second supply node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
Specification