Architecture of a PLL with dynamic frequency control on a PLD

• US 6,690,224 B1
• Filed: 06/27/2001
• Issued: 02/10/2004
• Est. Priority Date: 06/27/2001
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Moore, Michael T.
• Primary Examiner(s): NGUYEN, MINH T
• Application Number:
  US09/893,161
• Time in Patent Office: 958 Days
• Field of Search: 327/291, 327/293-299, 327/147, 327/155-161, 375/376, 331/1.A, 331/DIG.2, 331/177.R, 713/501
• US Class Current: 327/296
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop

Abstract

An apparatus including a clock generating circuit and a programmable logic circuit. The clock generating circuit may be configured to generate one or more output signals in response to a reference signal and one or more control signals, wherein the output signals each have a frequency and a phase that are dynamically variable. The programmable logic circuit may be configured to generate one or more of the control signals and receive the one or more output signals.

Claims

1. An apparatus comprising:

a clock generating circuit configured to generate one or more output signals in response to a reference signal and one or more control signals, wherein said output signals each have a frequency and a phase that are dynamically variable;

a programmable logic circuit configured to generate one or more of said control signals and receive said one or more output signals; and

a plurality of tri-statable buffers coupling said output signals of said clock generating circuit to said programmable logic circuit, wherein said clock generating circuit is configured to (i) receive said one or more control signals (a) from an external source when in a first mode, (b) internally from said programmable logic circuit when in a second mode, and (c) from both said external source and internally from said programmable logic circuit when in a third mode and (ii) said tri-statable buffers are configured to present said output signals to said programmable logic circuit when said clock generating circuit is in a locked state.

2. The apparatus according to claim 1, wherein a default frequency and a default phase is set for each of said one or more output signals in response to configuration information stored within said apparatus.

3. The apparatus according to claim 1, wherein said programmable logic circuit is configured to adjust said frequency and/or phase in response to predetermine criteria for power conservation.

4. The apparatus according to claim 1, wherein said programmable logic circuit comprises a device selected from the group consisting of a programmable logic array, a complex programmable logic device, and a field programmable gate array.

5. The apparatus according to claim 1, wherein said clock generating circuit comprises a phase lock loop (PLL).

6. The apparatus according to claim 1, wherein said clock generating circuit comprises a delay lock loop (DLL).

7. The apparatus according to claim 1, wherein said one or more control signals are generated in response to information stored in a configuration register of said apparatus.

8. The apparatus according to claim 7, wherein said configuration register is accessible via a JTAG port.

9. The apparatus according to claim 1, wherein said one or more control signals are generated in response to one or more external signals.

10. An apparatus comprising:

means for generating one or more output signals in response to a reference signal and one or more control signals, wherein said output signals each having a frequency and a phase that is dynamically variable; and

means for implementing user defined logic configured to generate said one or more control signals and receive said one or more output signals, wherein said phase of said output signals is varied by selecting one of a plurality of phases from a multi-phase phase lock loop.

11. A method for dynamically changing a frequency and/or phase of a clock signal on a programmable logic device comprising the steps of:

(A) generating one or more output signals in response to a reference signal and one or more control signals, wherein said output signals each have a frequency and a phase that are dynamically variable;

(B) receiving said one or more of output signals; and

(C) generating one or more of said control signals in response to one or more predetermined logic expressions, wherein said phase of said output signals is varied by selecting one of a plurality of phases from a multi-phase phase lock loop.

12. The method according to claim 11, wherein the step (A) comprises the sub-step of:

storing a default phase and frequency for said one or more output signals.

13. The method according to claim 11, wherein the step (A) further comprises the sub-step of:

selecting a phase and/or frequency for one or more of said output signals that is different from said default value based on said one or more control signals.

14. The method according to claim 13, wherein said output signals are enabled in response to a lock signal.

15. The method according to claim 11, wherein the step (A) comprises the sub-steps of:

disabling said one or more output signals;

changing said phase and/or frequency of one or more of said output signals; and

enabling said one or more output signals.

16. The method according to claim 11, wherein said frequency of said output signals is varied by changing multiplier values of a phase lock loop.

17. The method according to claim 11, wherein said frequency of said output signals is varied by changing a divider value.

18. The method according to claim 11, wherein said phase of said output signals is varied by changing a delay value of a delay lock loop.