Sealing of cells having active backplanes

• US 6,690,444 B1
• Filed: 08/01/2001
• Issued: 02/10/2004
• Est. Priority Date: 12/19/1998
• Status: Expired due to Fees

• Current Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Original Assignee: Qinetiq Limited (QinetiQ Group PLC)
• Inventors: Crossland, William A, Wilkinson, Timothy D
• Primary Examiner(s): DUDEK, JAMES A
• Application Number:
  US09/868,220
• Time in Patent Office: 923 Days
• Field of Search: 349/153
• US Class Current: 349/153
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136 Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit G02F1/135 takes precedence

Abstract

In active semiconductor backplane (3), for example for a smectic liquid crystal cell, which comprises an array of electronic or elctrical elements in a first region (4), logic elements for addressing said array in a second region spaced from the first, and conductors coupling said first and second regions, the first and second regions are sufficiently widely spaced (21, 22) (providing a “glue lane”) to permit the presence of an adhesive sealing strip therebetween without substantial contact with the first and/or second regions, even when an opposed substrate is sealed thereto. The backplane may comprise spacers (25, 26) in the first region and/or glue lane.

Claims

1. A semiconductor backplane comprising:

spaced first and second regions,

an array of electronic or electrical elements in said first region,

logic elements for addressing said array in said second region, and

conductors coupling said first and second regions, wherein the first and second regions are spaced by at least 500 microns to permit the presence of an adhesive sealing strip therebetween without substantial contact with the first and second regions.

2. A backplane according to claim 1 wherein the backplane is an active backplane in which the array comprises active electronic elements.

3. A backplane according to claim 1 and comprising integral spacers distributed within said array.

4. A backplane according to claim 1 and comprising integral spacers distributed within said lane.

5. A backplane according to claim 4 wherein said integral spacers comprise at least two layers essentially of the same material and occurring in the same order as is found in at least one of the electrical or electronic elements of the backplane.

6. A backplane according to claim 5 wherein all the layers in the spacers correspond in material and order to those found in the said at least one electrical or electronic element.

7. A backplane according to claim 1 wherein said at least one electrical or electronic elements is a transistor.

8. A cell comprising a backplane as defined in claim 1, and an opposed electrode sealed thereto in spaced relation.

9. A cell according to claim 8 wherein liquid crystal material is located between the electrode and the backplane.

10. A cell according to claim 9 wherein the liquid crystal material has a smectic phase.

11. A cell according to claim 8 wherein at least one of said backplane and said opposed electrode is transparent or translucent.

12. A cell according to claim 8 wherein the backplane and opposed electrode have identical length and width, and are in complete register.

13. A cell according to claim 8 wherein at least one of the backplane and opposed electrode projects beyond the other on at least one edge thereof.

14. A cell according to claim 13 wherein only the backplane projects beyond the opposed electrode.

15. A method according to claim 13 wherein the backplane projects beyond the opposed electrode on two opposed edges.