Effective gate-driven or gate-coupled ESD protection circuit

• US 6,690,561 B2
• Filed: 11/20/2001
• Issued: 02/10/2004
• Est. Priority Date: 09/06/2001
• Status: Active Grant

• Current Assignee: Faraday Technology Corp.
• Original Assignee: Faraday Technology Corp.
• Inventors: Chang, Hung-Yi, Chuang, Chien-Hui, Hung, Kei-Kang
• Primary Examiner(s): SALATA, ANTHONY J
• Application Number:
  US09/990,453
• Publication Number:
  US 20030043523A1
• Time in Patent Office: 812 Days
• Field of Search: 361/103, 361/111, 361/54, 361/56, 361/91
• US Class Current: 361/111
• CPC Class Codes: H02H 3/006 Calibration or setting of parameters
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

An ESD protection circuit, arranged between a first and second potential terminals, has a RC branch, a voltage adjuster circuit, and an ESD discharge transistor. The RC branch includes a resistor and a capacitor series connected from the first to the second potential terminal. The voltage adjuster circuit has a plurality of inputs connected to the RC branch, and the first and second potential terminals, and an output connected to a gate of the ESD discharge transistor to adjust the gate voltage thereof for obtaining a uniform turn on and optimal ESD robustness. The voltage adjuster circuit mainly includes a plurality of transistors that enable to effectively adjust the gate voltage with respect to high level of ESD stress.

Claims

1. A gate-driven or gate-coupling electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit is arranged between a first potential terminal and a second potential terminal of a principal circuit to bypass ESD current, the ESD protection circuit comprising:

a first resistor and a capacitor, the first resistor and the capacitor are series connected between the first potential terminal and the second potential terminal, wherein the first resistor and the capacitor we connected to each other via a first connection node;

at least an inverter, wherein the inverter has a first input connected to the first potential terminal, a second input connected to the second potential terminal, a third input connected to the first connection node, and an output;

a voltage clamping transistor having a first source, a first drain, and a first gate, wherein the first drain and the first source respectively connect from the output of the inverter to either the first or second potential terminal, and the first gate is connected to either the first or second potential terminal via a second resistor; and

an ESD discharge transistor having a second source, a second drain, and a second gate, wherein the second drain and the second source respectively connect from the first potential terminal to the second potential terminal to discharge ESD current, and the second gate is connected to the output of the inverter and to the first drain of the voltage clamping transistor, whereby the voltage of the second gate is adjusted by means of the inverter and the voltage clamping transistor to obtain an optimal ESD robustness and an uniform turn on of the ESD discharge transistor.

2. The ESD protection circuit of claim 1, wherein the inverter further comprises:

a first NMOS transistor having a third source, a third drain, and a third gate, wherein the third gate is connected to the first connection node, the third source is connected to the second potential terminal, and the third drain is respectively connected to the first drain of the voltage clamping transistor and the second gate of the ESD discharge transistor; and

a first PMOS transistor having a fourth source, a fourth drain, and a fourth gate, wherein the fourth gate is connected to the third gate of the first NMOS transistor and to the first connection node, the fourth drain is connected to the first potential terminal, and the fourth source is connected to the third drain of the first NMOS transistor.

3. The ESD protection circuit of claim 1, wherein the voltage clamping transistor includes either a PMOS transistor or a NMOS transistor.

4. The ESD protection circuit of claim 1, wherein the capacitor further includes a MOS structure.

5. The ESD protection circuit of claim 1, wherein the ESD discharge transistor includes a PMOS transistor or a NMOS transistor.

6. A gate-driven or gate-coupling electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit is arranged between a first potential terminal and a second potential terminal of a principal circuit to bypass ESD current, the ESD protection circuit comprising:

a first resistor and a capacitor, the first resistor and the capacitor are series connected between the first potential terminal and the second potential terminal, wherein the first resistor and the capacitor are connected to each other via a first connection node;

an ESD discharge transistor having a first source, a first drain, and a first gate, wherein the first drain and the first source respectively connect from the first potential terminal to the second potential terminal to shunt ESD current;

a first NMOS transistor having a second source, a second drain, and a second gate; and

a first PMOS transistor having a third source, a third drain, and a third gate, wherein the second gate and the third gate are respectively connected to each other and to the first connection node, and the second source, the second drain, the third source, and the third drain are connected in a connection chain from the first potential terminal to the second potential terminal, wherein the second source and the second drain are connected to each other and to the first gate of the ESD discharge transistor; and

at least a set of diodes, wherein the set of diodes is electrically placed in the connection chain so that the first PMOS transistor and the set of diodes can adjust the voltage of the first gate of the ESD discharge transistor to obtain an optimal ESD robustness and an uniform turn on of the ESD discharge transistor.

7. The ESD protection circuit of claim 6, wherein an additional set of diodes is electrically arranged between the first gate of the ESD discharge transistor and either the first or second potential terminal.

8. The ESD protection circuit of claim 6, wherein the capacitor includes a MOS structure.

9. A gate-driven or gate-coupling electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit is arranged between a first potential terminal and a second potential terminal of a principal circuit to bypass ESD current, the ESD protection circuit comprising:

a first resistor and a capacitor, the first resistor and the capacitor are series connected between the first potential terminal and the second potential terminal, wherein the first resistor and the capacitor are connected to each other via a first connection node;

an ESD discharge transistor having a source, a drain, and a gate, wherein the drain is connected to the first potential terminal and the source is connected to the second potential terminal to discharge ESD current; and

a voltage adjuster circuit, the voltage adjuster circuit has a first input port connected to the first potential terminal, a second input port connected to the second potential terminal, a third input connected to the first connection node, and an output connected to the gate of the ESD discharge transistor, wherein the voltage adjuster circuit includes a plurality of transistors electrically arranged to respectively turn off the ESD discharge transistor when no electrostatic discharge contacts with either the first or second potential terminal, and adjust the gate voltage of the ESD discharge transistor to obtain a uniform turn on and an optimal ESD robustness of the ESD discharge transistor when an electrostatic discharge contacts with the first or second potential terminal,

wherein the voltage adjuster circuit also comprises a MOS transistor having a source electrode and a drain electrode counted between the gate of the ESD discharge transistor and one of the first and second potential terminals, wherein a gate electrode of the MOS transistor is coupled to one of the first and second potential terminals via a resistor.

10. The ESD protection circuit of claim 9, wherein the voltage adjuster circuit includes a plurality of NMOS and PMOS transistors that are electrically arranged in inverter configuration.

11. The ESD protection circuit of claim 9, wherein the voltage adjuster circuit includes at least a set of diodes.

12. A gate-driven or gate-coupling electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit is arranged between a first potential terminal and a second potential terminal of a principal circuit to bypass ESD current, the ESD protection circuit comprising:

a first resistor and a capacitor, the first resistor and the capacitor are series connected between the first potential terminal and the second potential terminal, wherein the first resistor and the capacitor are connected to each other via a first connection node;

a plurality of ESD discharge transistors, wherein each ESD discharge transistor has a first drain connected to the first potential terminal, a first source connected to the second potential terminal, and a first gate;

a plurality of inverters, wherein each inverter has a first input connected to the first potential terminal, a second input connected to the second potential terminal, a third input, and an output connected to the first gate of one ESD discharge transistor, the inverters are connected to one another via connecting the output of one inverter to the third input of another inverter, wherein the third input of one of the inverters is further connected to the first connection node; and

a plurality of voltage clamping transistors, wherein each voltage clamping transistor has a second drain connected to the first gate of one ESD discharge transistor, a second source connected to either the first or second potential terminal, and a second gate connected to either the first or second potential terminal via a second resistor, so that each voltage clamping transistor and each inverter can adjust the voltage of the first gate of one ESD discharge transistor to obtain an uniform turn and an optimal ESD robustness of the ESD discharge transistor.

13. The ESD protection circuit of claim 12, wherein the voltage clamping transistors include PMOS and NMOS transistors.

14. The ESD protection circuit of claim 12, wherein the ESD discharge transistors includes NMOS transistors or PMOS transistors.

15. The ESD protection circuit of claim 12, wherein each inverter further comprises:

a first NMOS transistor having a third source, a third drain, and a third gate, wherein the third gate is connected to either the first connection node or the output of another inverter, the third source is connected to the second potential terminal, and the third drain is respectively connected to the second drain of one voltage clamping transistor and the first gate of one ESD discharge transistor; and

a first PMOS transistor having a fourth source, a fourth drain, and a fourth gate, wherein the fourth gate is connected to the third gate of the NMOS transistor, the fourth drain is connected to the first potential terminal, and the fourth source is connected to the third drain of the first NMOS transistor.

16. A gate-driven or gate-coupling electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit is arranged between a first potential terminal and a second potential terminal of a principal circuit to bypass ESD current, the ESD protection circuit comprising:

a first resistor and a capacitor, the first resistor and the capacitor are series connected between the first potential terminal and the second potential terminal, wherein the first resistor and the capacitor are connected to each other via a first connection node;

a plurality of ESD discharge transistors, wherein each ESD discharge transistor has a drain connected to the first potential terminal, a source connected to the second potential terminal, and a gate; and

a plurality of voltage adjuster circuits, each voltage adjuster circuit has a first input port connected to the first potential terminal, a second input port connected to the second potential terminal, a third input, and an output connected to the gate of one ESD discharge transistor, the voltage adjuster circuits are connected to one another via connecting the third input of one voltage adjuster circuit to the output of another voltage adjuster circuit, wherein the third input of one of the voltage adjuster circuits is further connected to the first connection node, each voltage adjuster circuit further includes a plurality of transistors electrically arranged to adjust the gate voltage of the ESD discharge transistor for obtaining a uniform turn on and an optimal ESD robustness of the ESD discharge transistors when an electrostatic discharge contacts with the first or second potential terminal,

wherein each of the voltage adjuster circuits also comprises a MOS transistor having a source electrode and a drain electrode coupled between the gate of the ESD discharge transistor and one of the first and second potential terminals, wherein a gate electrode of the MOS transistor is coupled to one of the first and second potential terminals via a resistor.

17. The ESD protection circuit of claim 16, wherein each voltage adjuster circuit includes a plurality of NMOS and PMOS transistors that are electrically arranged in inverter configuration.

18. A gate-driven or gate-coupling electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit is arranged between a first potential terminal and a second potential terminal of a principal circuit to bypass ESD current, the ESD protection circuit comprising:

a first resistor and a capacitor, the first resistor and the capacitor are series connected between the first potential terminal and the second potential terminal, wherein the first resistor and the capacitor are connected to each other via a first connection node;

an ESD discharge transistor, wherein the ESD discharge transistor has a drain connected to the first potential terminal, a source connected to the second potential terminal via a first voltage clamp, and a gate connected to the source via a second voltage clamp; and

an inverter, wherein the inverter has a first input port connected to the first potential terminal, a second input port connected to the second potential terminal, a third input connected to the first connection node, and an output connected to the gate of the ESD discharge transistor, so that the inverter and the first and second voltage clamps can adjust the gate voltage of the ESD discharge transistor to obtain an uniform turn on and optimal ESD robustness of the ESD discharge transistor.

19. The ESD protection circuit of claim 18, wherein the first voltage clamp includes a resistor or a set of diodes.

20. The ESD protection circuit of claim 18, wherein the second voltage clamp includes a set of diodes.