Video encoding and video/audio/data multiplexing device

• US 6,690,726 B1
• Filed: 04/06/2000
• Issued: 02/10/2004
• Est. Priority Date: 04/06/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Yavits, Leonid, Morad, Amir
• Primary Examiner(s): Kelley, Chris
• Assistant Examiner(s): VO, TUNG T
• Application Number:
  US09/543,904
• Time in Patent Office: 1,405 Days
• Field of Search: H04/B.166, 375/240, 375/240.01, 375/240.02, 375/240.11, 375/240.12, 375/240.13, 224/014, 224/015, 224/016, 224/017, 224/018, 224/019, 370/468, 370/477, 370/537, 370/538
• US Class Current: 375/240.12
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

A buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Claims

1. A single chip digital signal processing device for real time video/audio compression, said device comprising:

a plurality of processors, wherein said plurality of processors comprise;

a video input processor which receives, analyzes, scales and processes a digital signal,

a motion estimation processor which receives said processed signal, produces a motion analysis therefrom;

a digital signal processor which receives said processed signal, and according to said motion analysis, compresses said processed signal and produces a compressed processed signal,

a bitstream processor which receives and formats said compressed processed signal; and

a multiplexing processor which multiplexes plurality of digital signals and produces a multiplexed stream;

wherein said motion estimation processor operates on a macroblock a of frame I, said digital signal processor operates on macroblock of frame K, said bitstream processor operates on macroblock c of frame I, said multiplexing processor operates on frame J, wherein a≧

b≧

c, and I≧

J; and

wherein processing and transfer of said signals within said device is done in a macroblock-by-macroblock processing.

2. A device according to claim 1, further comprising:

a memory controller connected to said plurality of processors, wherein said memory controller controls data communication among said digital signal processor, said motion estimation processor, said video input processor and an external storage unit.

3. A device according to claim 1, further comprising:

a global controller which controls and schedules said video input processor, said motion estimation processor, said digital signal processor, said bitstream processor, said multiplexing processor and said memory controller.

4. A device according to claim 1, wherein said motion estimation processor, said digital signal processor, said video input processor, said bitstream processor and said multiplexing processor operate in parallel.

5. A device according to claim 1, wherein said video input processor comprises:

a capture unit which acquires a multiple frame video signal;

a video storage which buffers said multiple frame video signal thereby allowing adjustment between an internal video rate and an external data communication rate;

a pre-encoding processor which receives said multiple frame video signal from said capture unit and produces statistical analysis of said multiple frame video signal;

a scaler which receives said multiple frame video signal from said pre-encoding processor and modifies picture resolution;

a video processor which processes said multiple video signal, and;

a controller which controls and schedules said capture unit, said pre-encoding processor, said scaler, said video processor and said video storage.

6. A device according to claim 5, wherein said multiple frame video signal is acquired from at least one of the following:

a video interface and a host interface.

7. A device according to claim 5, further comprising:

an input storage unit which buffers said multiple frame video signal, thereby adjusting between external communication rate and internal video rate.

8. A device according to claim 1, wherein said video input processor operates on frame K such that K≧

I≧

J.

9. A device according to claim 1, wherein said multiplexing processor comprises:

a first video storage which buffers a compressed video bitstream, and which transfers said compressed video bitstream to said external memory unit, thereby adjusting between internal multiplexor processing rate and external communication rate;

a second video storage which reads from said memory unit said compressed video bitstream, and which buffers said compressed video bitstream, thereby adjusting between said external communication rate and said multiplexor processing rate;

an audio/data storage which buffers said digitized audio/data signal and which transfers said digitized audio/data signal to said processor, thereby adjusting between said external audio rate and said multiplexor processing rate;

a processor connected to said first and second video storage, said audio/data storage and said output storage, and which produces a multiplexed video/audio data stream, and;

an output storage which buffers said multiplexed video/audio/data stream, thereby adjusting between multiplexed video/audio/data stream rate and external communication rate.