Apparatus and method for receiving multiple data streams

• US 6,690,926 B2
• Filed: 03/06/2001
• Issued: 02/10/2004
• Est. Priority Date: 05/28/1998
• Status: Expired due to Fees

• Current Assignee: Northpoint Technology Limited
• Original Assignee: Northpoint Technology Limited
• Inventors: Tawil, Saleem, Tawil, Carmen
• Primary Examiner(s): Maung, Nay
• Assistant Examiner(s): Lee, John J
• Application Number:
  US09/800,354
• Publication Number:
  US 20010008835A1
• Time in Patent Office: 1,071 Days
• Field of Search: 455/277.1, 455/277.2, 455/272, 455/3.02, 455/3.04, 455/3.06, 455/278.1, 455/133, 455/180.1, 455/323, 455/132, 455/136, 455/137, 370/351
• US Class Current: 455/277.1
• CPC Class Codes: H04B 7/18523 Satellite systems for providing broadcast service to terrestrial stations, i.e. broadcast satellite service arrangements specially adapted for satellite broadcast receiving H04H40/90; picture transmission via satellite H04N1/00103; television transmission via satellite H04N7/20
• CPC Class Codes: H04H 40/90 specially adapted for satellite broadcast receiving
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4382 Demodulation or channel decoding, e.g. QPSK demodulation analog front ends or means for connecting modulators, demodulators or transceivers to a transmission line H04L27/0002
• CPC Class Codes: H04N 21/4622 Retrieving content or additional data from different sources, e.g. from a broadcast channel and the Internet web site content organization and management for information retrieval from the Internet G06F16/958; transmission by internet of broadcast information H04H60/82; stock exchange data over packet-switching network H04L12/1804; push services including data channel over packet-switching network H04L12/1859
• CPC Class Codes: H04N 7/20 Adaptations for transmission via a GHz frequency band, e.g. via satellite

Abstract

A multiple data stream processing arrangement includes a receiver/signal processor (14) and a plurality of signal input paths (11, 12) which meet at a junction (36). A junction output from the junction (36) provides a single input to the receiver/signal processor (14). A switching arrangement (16) is associated with the plurality of signal input paths (11, 12). The switching arrangement (16) includes a switch (31, 32) connected in each signal input path (11, 12). Each switch (31, 32) responds to an enable signal to allow a data stream applied to the respective input path (11, 12) to pass on to the junction (36) and to the receiver/signal processor (14). Only one signal input path (11, 12) and respective switch (31, 32) is enabled at any given time.

Claims

1. An apparatus for receiving a first stream of data signals at a first input and for receiving a second stream of data signals at a second input, the apparatus comprising:

(a) a first switch connected to the first input and having a first switch output, the first switch for passing the first stream of data signals from the first input to the first switch output in response to a first switch enable signal applied to an enable input associated with the first switch;

(b) a second switch connected to the second input and having a second switch output, the second switch for passing the second stream of data signals from the second input to the second switch output in response to a second switch enable signal applied to an enable input associated with the second switch;

(c) a controller for selectively applying the first switch enable signal and for selectively applying the second switch enable signal; and

(d) a memory device connected to the controller, the memory device storing signal path information for a plurality of channel outputs, the signal path information for each respective one of the channel outputs relating the respective channel output to one of the first switch or second switch which must be enabled to pass data signals from which the respective channel output can be produced.

2. The apparatus of claim 1 wherein the memory device also stores signal processing information for each channel output, the signal processing information comprising information required by a signal processor to produce the respective channel output from the respective stream of data signals.

3. The apparatus of claim 2 wherein the signal processor includes:

(a) a full rate tuner and down converter;

(b) a demodulator;

(c) a forward error correction decoder; and

(d) a demultiplexer/format decoder.

4. The apparatus of claim 1 further including:

(a) a satellite receiving antenna oriented to receive signals transmitted directly from a satellite transmitter, the first stream of data signals including data received through the satellite receiving antenna; and

(b) a terrestrial receiving antenna oriented to receive signals transmitted directly from a terrestrial transmitter, the second stream of data signals including data received through the terrestrial receiving antenna.

5. The apparatus of claim 1 further including:

(a) a satellite receiving antenna oriented to receive signals transmitted directly from a satellite transmitter, the first stream of data signals being produced from data received through the satellite receiving antenna; and

(b) a terrestrial receiving antenna oriented to receive signals transmitted directly from a terrestrial transmitter, the second stream of data signals being produced from data received through the terrestrial receiving antenna.

6. The apparatus of claim 1 wherein:

(a) the first stream of data signals includes signals on a plurality of first carrier frequencies; and

(b) the second stream of data signals includes signals on at least one of the first carrier frequencies.

7. The apparatus of claim 1 wherein the first stream of data signals and the second stream of data signals each include signals on a common carrier frequency.

8. An apparatus including:

(a) a first switch connected to a first input and having a first switch output, the first switch for passing a first stream of data signals from the first input to the first switch output in response to a first switch enable signal applied to an enable input associated with the first switch;

(b) a second switch connected to a second input and having a second switch output, the second switch for passing a second stream of data signals from the second input to the second switch output in response to a second switch enable signal applied to an enable input associated with the second switch;

(c) a memory device storing signal path information for a plurality of channel outputs, the signal path information for each respective one of the channel outputs relating the respective channel output to one of the first switch or second switch which must be enabled to pass data signals from which the respective channel output can be produced; and

(d) a controller operatively connected to the memory device, the first switch, and the second switch for selectively producing either the first switch enable signal or the second switch enable signal in response to signal path information obtained from the memory device.

9. The apparatus of claim 8 wherein the memory device also stores signal processing information for each channel output, the signal processing information including information enabling a signal processor to produce the respective channel output from the respective stream of data signals.

10. The apparatus of claim 9 wherein the signal processor includes:

(a) a tuner;

(b) a demodulator;

(c) a forward error correction decoder; and

(d) a demultiplexer/format decoder.

11. The apparatus of claim 8 wherein:

(a) the first data stream includes signals on a plurality of first carrier frequencies; and

(b) the second data stream includes signals on at least one of the first carrier frequencies.

12. The apparatus of claim 8 wherein the first data stream and the second data stream include signals on a common carrier frequency.

13. An apparatus including:

(a) a first switch connected to a first input and having a first switch output, the first switch for passing a first stream of data signals from the first input to the first switch output in response to a first switch enable signal applied to an enable input associated with the first switch;

(b) a second switch connected to a second input and having a second switch output, the second switch for passing a second stream of data signals from the second input to the second switch output in response to a second switch enable signal applied to an enable input associated with the second switch;

(c) a satellite receiving antenna oriented to receive signals transmitted directly from a satellite transmitter, the first stream of data signals including data received through the satellite receiving antenna;

(d) a terrestrial receiving antenna oriented to receive signals transmitted directly from a terrestrial transmitter, the second stream of data signals including data received through the terrestrial receiving antenna; and

(e) a controller operatively connected to the first switch and the second switch for selectively producing either the first switch enable signal or the second switch enable signal in response to signal path information for a particular channel output, the signal path information indicating which of the first switch or second switch must be enabled to pass data from which the particular channel output can be produced.

14. The apparatus of claim 13 further including a memory device storing signal path information for the particular channel output along with a plurality of additional channel outputs, the signal path information for each respective one of the channel outputs relating the respective channel output to one of the first switch or second switch which must be enabled to pass data signals from which the respective channel output can be produced.

15. The apparatus of claim 14 wherein the memory device also stores signal processing information for each channel output, the signal processing information comprising information required by a signal processor to produce the respective channel output from the respective stream of data signals.

16. The apparatus of claim 15 wherein the signal processor includes:

(a) a tuner;

(b) a demodulator;

(c) a forward error correction decoder; and

(d) a demultiplexer/format decoder.

17. The apparatus of claim 13 wherein:

(a) the first data stream includes signals on a plurality of first carrier frequencies; and

(b) the second data stream includes signals on at least one of the first carrier frequencies.

18. The apparatus of claim 13 wherein the first data stream and the second data stream each include signals on a common carrier frequency.