Synchronizing clock enablement in an electronic device

• US 6,691,071 B2
• Filed: 05/13/2002
• Issued: 02/10/2004
• Est. Priority Date: 05/13/2002
• Status: Active Grant

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Leyh, Arthur C., Koh, Bokchain, Kerr, John S.
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): O MALLEY, MARY CATHERINE
• Application Number:
  US10/144,613
• Publication Number:
  US 20030212531A1
• Time in Patent Office: 638 Days
• Field of Search: 702/57, 702/79, 702/89, 702/122, 702/124-125, 702/176-178, 702/186-188, 455/403, 455/502, 455/151.1, 455/352, 713/320, 713/322-323, 713/400
• US Class Current: 702/188
• CPC Class Codes: G06F 1/3209 Monitoring remote activity, e.g. over telephone lines or network connections
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: H04B 2215/066 by stopping a clock generator
• CPC Class Codes: H04W 52/0287 changing the clock frequency of a controller in the equipment
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A method of synchronizing enablement of a common clock for a main and a second processor in an electronic device having a low-power mode includes a first step of completing a communication activity by the main processor. A next step includes monitoring a clock enable signal from the second processor. A next step includes comparing the timing of the second processor with the known timing of the main processor if the second processor does not have the clock enabled in the monitoring step. A next step includes calculating the the timing needed to synchronize the clock enablement by the second processor to that of the main processor. A next step includes powering up and powering down the second processor under control by the main processor to synchronize the periodic timing of the second processor to that of the main processor.

Claims

1. A method of synchronizing enablement of a clock commonly connected to a main and a second processor both configured for wireless communication within an electronic device having a low-power mode, the method comprising the steps of:

completing a communication activity by one of the processors;

monitoring a clock enable signal from each of the processors to the common clock;

comparing the clock-enabled timing of one of the processors with the known clock-enabled timing of the other processor;

calculating the the timing needed to synchronize the clock enablement of the processors; and

synchronizing the periodic timing of the processors.

2. The method of claim 1, wherein the second processor has variable power up times and the main processor has fixed periodic power up times, and wherein the synchronizing step includes powering up and powering down the second processor under control of the main processor to synchronize the timing of the processors.

3. The method of claim 2, wherein the second processor is operable in a local area network communication system, and wherein the monitoring step include monitoring a clock enable signal from the second processor and the comparing step includes the other processor being the main processor.

4. The method of claim 2, wherein the second processor has a minimum wake up time period that is greater than a minimum wake up time period of the main processor.

5. The method of claim 1, wherein the main processor is operable in a local area network communication system.

6. The method of claim 1, wherein the second processor has a minimum wake up time period that is less than a minimum wake up time period of the main processor.

7. The method of claim 1, further comprising the step of detecting when an active communication is made by either of the processors, wherein the above steps are repeated.

8. The method of claim 1, wherein after the monitoring step further comprising the step of waiting until the second processor goes through one communication cycle to measure its timing.

9. The method of claim 1, wherein the calculating step includes calculating the timing such that the clock enablement signals of the main and second processors will overlap in time.

10. The method of claim 1, wherein if the main processor is out of service, then the second processor controls the timing of the second processor unless it is out of service itself.

11. A method of synchronizing enablement of a clock commonly connected to a main processor operable in a wide area radio communication system and a second processor operable in a local area network communication system within an electronic device having a low-power mode, the method comprising the steps of:

completing a communication activity by one of the processors;

monitoring a clock enable signal from the second processor to the common clock;

comparing the timing of the second processor with the known timing of the main processor if the second processor does not have the common clock enabled in the monitoring step;

calculating the timing needed to synchronize the clock enablement by the second processor to that of the main processor; and

powering up and powering own the second processor under control of the main processor to synchronize the periodic timing of the second processor to that of the main processor.

12. The method of claim 11, wherein the second processor has a minimum wake up tune period that is greater than a minimum wake up time period of the main processor.

13. The method of claim 11, wherein the second processor has a minimum wake up time period that is less than a minimum wake up time period of the main processor.

14. The method of claim 11, wherein after the monitoring step further comprising the step of waiting until the second processor goes through one communication cycle to measure its timing.

15. The method of claim 11, wherein the calculating step includes calculating the timing such that the clock enablement signals of the main and second processors will overlap in time.

16. The method of claim 11, wherein in the main processor is operable in at least one of a WCDMA, CDMA, TDMA and GSM communication system.

17. The method of claim 11, wherein in the second processor is operable in at least one of a Bluetooth™

and IEEE 802.11 communication system.

18. A method of synchronizing enablement of a clock commonly connected to a main processor operable in a wide area radio communication system and a second processor operable in a local area network communication system within an electronic device having a low-power mode, the method comprising the steps of:

completing a communication activity by the main processor;

monitoring a clock enable signal from the second processor to the common clock;

waiting until the second processor goes through one communication cycle before measuring its timing;

comparing the timing of the second processor with the known timing of the main processor if the second processor does not have the common clock enabled in the monitoring step;

calculating the the timing needed to synchronize the clock enablement by the second processor to that of the main processor;

powering up and powering down the second processor under control of the main processor to synchronize the periodic timing of the second processor to that of the main processor; and

detecting when an active communication is made by either of the processors, wherein all the above steps are repeated.

19. The method of claim 18, wherein the second processor has a minimum wake up time period that is greater than a minimum wake up time period of the main processor.

20. The method of claim 19, wherein the calculating step includes calculating the timing such that the clock enablement signals of the main and second processors will overlap in time.