Method and system for analyzing test coverage

• US 6,691,079 B1
• Filed: 05/28/1999
• Issued: 02/10/2004
• Est. Priority Date: 05/28/1999
• Status: Expired due to Term

• Current Assignee: Synopsys Incorporated
• Original Assignee: SpringSoft, Inc. (Synopsys Incorporated)
• Inventors: Lai, Ming-chih, Juan, Hsing-ming
• Primary Examiner(s): Broda, Samuel
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US09/322,185
• Time in Patent Office: 1,719 Days
• Field of Search: 703/14, 703/15, 703/16, 714/738, 714/739, 716/4, 716/18
• US Class Current: 703/16
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method for determining test coverage of an original high level language description which represents an electrical circuit by the data of at least one dump file exported by a simulation program, the original high level description having at least one executable assignment statement which models the circuit, the at least one executable assignment statement having a left side and a right side separated by an assignment operator, the left side being a variable, and the right side being an expression which has a set of at least one variable and at least one logic operator, the expression on the right side, when evaluated, determining a value to be assigned to the variable on the left side, the data of the dump file consisting of the values of all the variables of the originals high level language description between a simulation start time instant and a simulation end time instant the method comprising: a description importing step for importing the original high level language description to form a design database; a dump file importing step for importing the dump file; and a test coverage determining step for determining the test coverage of the original high level language description by the values of the variables at all the time instants from the simulation start time instant to the simulation end time instant.

Claims

1. A method for determining whether a circuit simulator executed various statements included in a high level language (HLL) program while performing a simulation of an electrical circuit modeled by the HLL program, wherein the statements include a root event statement unconditionally directing the circuit simulator to execute a next one of the statements of the program, statements directing the circuit simulator to set states of variables representing circuit signals, and statements indicating a condition under which program execution is to flow to another statement of the program, and wherein the circuit simulator generated a dump file indicating states of variables controlled by statements as functions of time, the method comprising the steps of:

a. processing the HLL program to generate a directed graph comprising program flow information, a root vertex representing the root event statement, and a plurality of other vertices, each representing a separate other statement of the HLL program, wherein the program flow information indicates directions of HLL program flow between statements represented by the vertices,

b. processing the dump file to determine points in simulated time at which a particular variable changed state, and

c. identifying which of the vertices of the directed graph represent statements that the circuit simulator executed in order to determine how to set the state of the particular variable at each of the points in simulated time.

2. The method in accordance with claim 1 further comprising the step of:

d. based on the program flow information included in the directed graph, identifying vertices representing statements that must have been executed by the circuit simulator for the circuit simulator prior to executing any statement represented by any vertex identified at step c.

3. The method in accordance with claim 2 further comprising the step of:

e. determining whether a particular vertex of the directed graph generated at step a was identified at either of steps c and d as representing a statement that the circuit simulator executed.

4. The method in accordance with claim 3 further comprising the step of:

f. iteratively repeating steps b through e with a separate variable being selected as the particular variable during each iteration of steps b through e.

5. The method in accordance with claim 2 further comprising the step of:

e. determining whether a particular vertex was identified at step c as representing a statement that the circuit simulator executed, and whether that statement caused the circuit simulator to set the particular variable to each one of its possible states at said points in simulated time.

6. The method in accordance with claim 2 further comprising the step of:

e. iteratively repeating steps b through d with a separate variable being selected as the particular variable for each iteration of steps b through d.

7. The method in accordance with claim 6 wherein one of the statements is a conditional branch statement containing an expression the circuit simulator evaluates to determine a next statement to be executed, and wherein the method further comprises the step of:

f. determining from the program flow information included in the directed graph, whether each vertex of the directed graph representing a statement that may be executed immediately after the conditional branch statement was identified during any iteration step c or d as having been executed by the circuit simulator.

8. The method in accordance with claim 1

wherein one of the statements is a trigger event statement indicating that a condition under which the circuit simulator is to execute a next statement of the program is a next occurrence of an event, and

wherein the vertex representing that triggered event statement includes timing information indicating each point in simulated time at which that event occurs.

9. A method for determining which portions of a high level language (HLL) program a circuit simulator executed while performing a simulation of an electrical circuit modeled by the HLL program,

wherein the HLL program includes a plurality of event units, each comprising a plurality of statements including a root event statement unconditionally directing the circuit simulator to execute a next statement of the event unit during the simulation,

wherein at least one event unit also comprises at least one variable assignment statement directing the circuit simulator to set at least one variable to a particular state determined by evaluating an assignment expression included in the variable assignment statement,

wherein at least one event unit comprises at least one conditional branch statement directing the circuit simulator to evaluate a branching expression included in the conditional branch statement to determine another statement of that event unit to next execute, and

wherein at least one event unit comprises at least one triggered event statement directing the circuit simulator execute a next statement of the event unit upon a next occurrence of a triggering event identified by the triggering event statement;

wherein the circuit simulator generates a dump file indicating states of variables controlled by the statements of the event units as functions of simulated time, the method comprising the steps of;

a. processing the HLL program to generate for each event unit, a separate directed graph comprising a root vertex representing the root event statement of that event unit, a separate vertex representing each other statement of the event unit, and comprising program flow information indicating directions of HLL program flow between the statements represented by the directed graph'"'"'s vertices,

b. processing the dump file to determine points in said simulated time at which a particular variable changed state, and

c. determining which of the vertices of any directed graph generated at step a, represents a statement that must have been executed by the circuit simulator for the circuit simulator to have changed the states of the particular variable any of said points in said simulated time.

10. The method in accordance with claim 9

wherein each vertex representing a triggered event statement includes timing information defining a point in simulated time of each occurrence of a triggering event referenced by the triggered event it represents.

11. The method in accordance with claim 10 wherein step c comprises the substeps of:

c1. identifying each vertex of any directed graph generated at step a representing a statement which, when executed, directed the circuit simulator to set the state of the particular variable at any one of the particular points in simulated time, and

c2. identifying any vertex of any directed graph generated at step a which, based on the program flow information included in that directed graph, represents a statement the circuit simulator must have executed in order to have executed a statement represented by any vertex identified at step c1.

12. The method in accordance with claim 10 further comprising the step of:

d. determining whether a particular vertex of any directed graph generated at step a was identified at step c as representing a statement that must have been executed.

13. The method in accordance with claim 10 further comprising the step of:

d. determining whether a particular vertex of any directed graph generated at step a was identified at step c as representing a statement that must have been executed and whether that statement caused the circuit simulator to set the particular variable to each one of its possible states at said points in said simulated time.

14. The method in accordance with claim 13 further comprising the step of:

e. iteratively repeating steps b, c and d with a separate variable being selected as the particular variable for each iteration of steps b, c and d.

15. The method in accordance with claim 10 further comprising the step of:

d. iteratively repeating steps b and c with a separate variable being selected as the particular variable for each iteration of steps b and c.

16. The method in accordance with claim 15 further comprising the step of:

e. determining whether every vertex of a directed graph representing a statement that the program flow information indicates the circuit simulator can execute immediately following a conditional branch statement was identified during at least one iteration of step c.