Computing circuit, computing apparatus, and semiconductor computing circuit

• US 6,691,145 B1
• Filed: 07/13/2000
• Issued: 02/10/2004
• Est. Priority Date: 08/09/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Technology Academic Research Center
• Original Assignee: Semiconductor Technology Academic Research Center
• Inventors: Konda, Masahiro, Ohmi, Tadahiro, Shibata, Tadashi
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/615,754
• Time in Patent Office: 1,307 Days
• Field of Search: 708/801, 708/3, 708/201, 708/671, 340/146.2
• US Class Current: 708/801
• CPC Class Codes: G06G 7/14 for addition or subtraction of vector quantities G06G7/22 ; computing the average by addition; differential amplifiers H03F3/45
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: H04N 19/94 Vector quantisation

Abstract

A computing circuit capable of computing an absolute difference with high-speed analog computation, a computing apparatus capable of computing the sum of absolute differences and a semiconductor computing circuit achievable with simple circuitry and suitable for use in such a computing circuit or apparatus. The computing circuit capable of computing the absolute difference includes a large input selection circuit 1 which outputs either a first signal or a second signal whichever is larger, a small input selection circuit 2 which outputs either the first and second signals whichever signal is smaller, and a subtraction circuit 3 which subtracts the output of the small input selection circuit 2 from the output of the large input selection circuit 1. The subtraction circuit 3 includes a capacitor 6, a first switch 4 provided between a first terminal of the capacitor 6 and the output of the large input selection circuit 1, a second switch 5 provided between the first terminal of the capacitor 6 and the output of the small input selection circuit 2, and a third switch 7 provided between a second terminal of the capacitor 6 and a terminal connected to a prescribed potential. The computing apparatus capable of computing the sum of absolute differences includes a plurality of such computing circuits, and computes the sum of the outputs of the computing circuits by using a summing circuit.

Claims

1. A computing circuit for computing an absolute difference between a first signal and a second signal, comprising:

a large input selection circuit which compares said first and second signals and outputs whichever signal is larger in signal value;

a small input selection circuit which compares said first and second signals and outputs whichever signal is smaller in signal value; and

a subtraction circuit for subtracting the output of said small input selection circuit from the output of said large input selection circuit, wherein said subtraction circuit comprises;

a capacitor;

a first switch provided between a first terminal of said capacitor and the output of said large input selection circuit;

a second switch provided between the first terminal of said capacitor and the output of said small input selection circuit; and

a third switch provided between a second terminal of said capacitor and a terminal connected to a prescribed potential, and wherein;

the absolute difference between said first signal and said second signal is output from said second terminal of said capacitor by first turning said first switch off and said third switch on, then turning said second switch on, and thereafter turning said third switch off, then turning said second switch off, and finally turning said first switch on.

2. A computing circuit as claimed in claim 1, wherein said second terminal of said capacitor is a floating gate, and wherein said floating gate is a gate of a source follower circuit, and said source follower circuit outputs the absolute difference between said first signal and said second signal.

3. A computing circuit for computing an absolute difference between a first signal and a second signal, comprising:

a large input selection circuit which compares said first and second signals and outputs whichever signal is larger in signal value;

a small input selection circuit which compares said first and second signals and outputs whichever signal is smaller in signal value; and

a subtraction circuit for subtracting the output of said small input selection circuit from the output of said large input selection circuit, wherein

said large input selection circuit is a circuit comprising two NMOS transistors connected in parallel and, by applying said first signal to a gate of one of said NMOS transistors and said second signal to a gate of the other of said NMOS transistors, said first signal or said second signal, whichever is larger, is output from a common source electrode, and

said small input selection circuit is a circuit comprising two NMOS transistors connected in series and, by applying said first signal to a gate of one of said NMOS transistors and said second signal to a gate of the other of said NMOS transistors, said first signal or said second signal, whichever is smaller, is output from a source electrode.

4. A computing circuit as claimed in claim 3, wherein

the gate of the NMOS transistor to which said first signal is applied in said large input selection circuit and the gate of the NMOS transistor to which said first signal is applied in said small input selection circuit are a floating gate connected in common to both of said NMOS transistors, and

said computing circuit includes a write circuit for writing a voltage to said floating gate.

5. A computing circuit for computing an absolute difference between a first signal and a second signal, comprising:

a large input selection circuit which compares said first and second signals and outputs whichever signal is larger in signal value;

a small input selection circuit which compares said first and second signals and outputs whichever signal is smaller in signal value; and

a subtraction circuit for subtracting the output of said small input selection circuit from the output of said large input selection circuit, wherein

said large input selection circuit is a circuit comprising two PMOS transistors connected in series and, by applying said first signal to a gate of one of said PMOS transistors and said second signal to a gate of the other of said PMOS transistors, said first signal or said second signal, whichever is larger, is output from a source electrode, and

said small input selection circuit is a circuit comprising two PMOS transistors connected in parallel and, by applying said first signal to a gate of one of said PMOS transistors and said second signal to a gage of the other of said PMOS transistors, said first signal or said second signal, whichever is smaller, is output from a common source electrode.

6. A computing circuit as claimed in claim 5, wherein

the gate of the PMOS transistor to which said first signal is applied in said large input selection circuit and the gate of the PMOS transistor to which said first signal is applied in said small input selection circuit are a floating gate connected in common to both of said PMOS transistors, and

said computing circuit includes a write circuit for writing a voltage to said floating gate.

7. A computing apparatus for computing the sum of absolute differences between corresponding signals in a first signal group and a second signal group each consisting of a predetermined number of signals, comprising:

computing circuits corresponding in number to said predetermined number of signals, each of said computing circuit comprising;

a large input selection circuit which compares said first and second signals and outputs whichever signal is larger in signal value;

a small input selection circuit which compares said first and second signals and outputs whichever signal is smaller in signal value; and

a subtraction circuit for subtracting the output of said small input selection circuit from the output of said large input selection circuit,

said subtraction circuit comprises;

a capacitor;

a first switch provided between a first terminal of said capacitor and the output of said large input selection circuit;

a second switch provided between the first terminal of said capacitor and the output of said small input selection circuit; and

a third switch provided between a second terminal of said capacitor and a terminal connected to a prescribed potential, and wherein;

the absolute difference between said first signal and said second signal is output from said second terminal of said capacitor by first turning said first switch off and said third switch on, then turning said second switch on, and thereafter turning said third switch off, then turning said second switch off, and finally turning said first switch on, and wherein;

said second terminal of each capacitor is connected in common.

8. A computing apparatus as claimed in claim 7, wherein said second terminal connected in common is a floating gate, and wherein said floating gate is a gate of a source follower circuit, and said source follower circuit outputs the sum of the absolute differences between said first signal group and said second signal group.

9. A computing apparatus for computing the sum of absolute differences between corresponding signals in a first signal group and a second signal group each consisting of a predetermined number of signals, comprising:

selection circuits corresponding in number to said predetermined number of signals, each selection circuit including a large input selection circuit for comparing said first and second signals and for outputting whichever signal is larger in signal value, and a small input selection circuit for comparing said first and second signals and for outputting whichever signal is smaller in signal value;

a large summing circuit for summing the outputs of said large input selection circuits in said predetermined number of selection circuits;

a small summing circuit for summing the outputs of said small input selection circuits in said predetermined number of selection circuits; and

a subtraction circuit for subtracting the output of said small summing circuit from the output of said large summing circuit.

10. A computing apparatus as claimed in claim 9, wherein

said large summing circuit comprises: first capacitors corresponding in number to said predetermined number of selection circuits and having first terminals connected to the respective outputs of said large input selection circuits in said predetermined number of selection circuits and second terminals connected together as a common second terminal;

a switch provided between said common second terminal and a terminal connected to a prescribed potential; and

a first output circuit for outputting a potential level of said common second terminal,

said small summing circuit comprises;

second capacitors corresponding in number to said predetermined number of selection circuits and having first terminals connected to the respective outputs of said small input selection circuits in said predetermined number of selection circuits and second terminals connected together as a common second terminal;

a switch provided between said common second terminal of said second capacitors and a terminal connected to a prescribed potential; and

a second output circuit for outputting a potential level of said common second terminal of said second capacitors, and

said subtraction circuit comprises;

a capacitor;

a first switch provided between a first terminal of said capacitor and the output of said first output circuit;

a second switch provided between the first terminal of said capacitor and the output of said second output circuit; and

third switch provided between a second terminal of said capacitor and a terminal connected to a prescribed potential, and wherein;

the sum of the absolute differences between corresponding signals in said first signal group and said second signal group is output from said second terminal of said capacitor by first turning said first switch off and said third switch on, then turning said second switch on, and thereafter turning said third switch off, then turning said second switch off, and finally turning said first switch on.

11. A semiconductor computing circuit which compares a first signal and a second signal and outputs whichever signal is larger in signal value and whichever signal is smaller in signal value, comprising:

first and second NMOS transistors connected in parallel; and

third and fourth NMOS transistors connected in series, and wherein;

said first and said third NMOS transistor share a common floating gate, and

by applying said second signal to the gates of said second and said fourth NMOS transistor after writing said first signal to said floating gate, said first signal or said second signal, whichever is larger, is output from a source electrode connected in common to said first and second NMOS transistors, while said first signal or said second signal, whichever is smaller, is output from a source electrode of said third and fourth NMOS transistors.

12. A semiconductor computing circuit which compares a first signal and a second signal and outputs whichever signal is larger in signal value and whichever signal is smaller in signal value, comprising:

first and second PMOS transistors connected in parallel; and

third

and fourth PMOS transistors connected in series, and wherein;

said first and said third PMOS transistor share a common floating gate, and

by applying said second signal to the gates of said second and said fourth PMOS transistor after writing said first signal to said floating gate, said first signal or said second signal, whichever is smaller, is output from a source electrode connected in common to said first and second PMOS transistors, while said first signal or said second signal, whichever is larger, is output from a source electrode of said third and fourth PMOS transistors.