DMA controller in which bus access ratio can be set

• US 6,691,182 B2
• Filed: 04/02/2001
• Issued: 02/10/2004
• Est. Priority Date: 07/04/2000
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kagemoto, Tetsuya
• Primary Examiner(s): HUYNH, KIM NGOC
• Application Number:
  US09/822,361
• Publication Number:
  US 20020004861A1
• Time in Patent Office: 1,044 Days
• Field of Search: 710/22, 710/26, 710/28, 710/107, 710/33
• US Class Current: 710/28
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/30 with priority control
• CPC Class Codes: G06F 2213/2804 Systems and methods for controlling the DMA frequency on an access bus

Abstract

A DMA controller includes: a bus availability frequency register setting a ratio of a bus access frequency of DMA transfer to a bus access frequency of another bus master; a DMA request detecting portion detecting a DMA request; a bus availability counter counting the bus access frequency in accordance with the ratio set in the bus availability frequency counter; a bus access request controlling portion controlling the bus access request based on the DMA request detected by the DMA request detecting portion and the counted result of the counter; and a DMA controlling portion controlling execution of DMA transfer. Thus, a band which allows another bus master to use a bus during DMA transfer can be predicted.

Claims

1. A direct memory access controller, comprising:

a register setting a ratio of a bus access frequency of direct memory access transfer to a bus access frequency of another bus master;

a direct memory access request detecting portion detecting a direct memory access request;

a counter counting a bus access frequency in accordance with said ratio set in said register;

a bus access request controlling portion controlling a bus access request based on said direct memory access request detected by said direct memory access request detecting portion and the counted result of said counter; and

a direct memory access controlling portion controlling execution of direct memory access transfer in accordance with a bus access grant.

2. The direct memory access controller according to claim 1, wherein said register includes a bus availability frequency register setting said bus access frequency of said another bus master, and

said counter includes a bus availability counter counting said bus access frequency of said another bus master in accordance with a value set in said bus availability frequency register.

3. The direct memory access controller according to claim 2, wherein said bus access request controlling portion outputs the bus access request in such a way that a ratio of a bus access frequency of said direct memory access controlling portion to said bus access frequency of said another bus master is 1:

N, where said value set in said bus availability frequency register is a positive integer N.

4. The direct memory access controller according to claim 2, wherein said register further includes a bus access frequency register setting said bus access frequency of said direct memory access controlling portion, and

said counter further includes a bus access counter counting said bus access frequency of said direct memory access controlling portion in accordance with said value set in said bus access frequency register.

5. The direct memory access controller according to claim 4, wherein said bus access request controlling portion outputs the bus access request in such a way that a ratio of said bus access frequency of said direct memory access controlling portion to said bus access frequency of said another bus master is M:

N, where said value set in said bus access frequency register is a positive integer M and said value set in said bus availability frequency register is a positive integer N.

6. The direct memory access controller according to claim 1, wherein said register includes

a bus access weight register setting a weight of bus access by said direct memory access controlling portion, and

a bus availability weight register setting a weight of bus access by said another bus master, and said counter includes

a bus access weight counter adding or subtracting values set in said bus access weight register and said bus availability weight register.

7. The direct memory access controller according to claim 6, wherein said bus access weight counter subtracts the value set in said bus access weight register every time the bus access by said direct memory access controlling portion is detected and adds said value set in said bus availability weight register every time the bus access by said another bus master is detected, and

said bus access request controlling portion asserts said bus access request when said value of said bus access weight counter is at least 0, and negates said bus access request when said bus access weight counter has a negative value.

8. The direct memory access controller according to claim 1, wherein said bus access request controlling portion inputs bus freedom information indicating absence of a bus access request from another bus master, and asserts said bus access request when said bus freedom information is asserted.

9. The direct memory access controller according to claim 1, wherein said register includes registers for a plurality of channels each setting a ratio of a bus access frequency of direct memory access transfer to a bus access frequency of another bus master, and

said counter includes a bus access weight counter adding and subtracting values in accordance with bus access of a channel executing direct memory access transfer of said plurality of channels and bus access by said another bus master.

10. A direct memory access transfer method, comprising the steps of:

setting a ratio of a bus access frequency of direct memory access transfer to a bus access frequency of another bus master;

detecting a direct memory access request;

counting a bus access frequency in accordance with said set ratio;

controlling a bus access request based on said detected direct memory access request and said counted result; and

controlling execution of direct memory access transfer in accordance with a bus access grant.

11. The direct memory access transfer method according to claim 10, wherein said step of setting said ratio includes the step of setting a bus access frequency of said another bus master, and

said step of counting said bus access frequency includes the steps of counting said bus access frequency of said another bus master in accordance with said set bus access frequency of said another bus master.

12. The direct memory access transfer method according to claim 11, wherein said step of controlling said bus access request includes the step of outputting the bus access request in such a way that said ratio of said bus access frequency of said direct memory access transfer to said bus access frequency of said another bus master is 1:

N, where said set bus access frequency of said another bus master is a positive integer N.

13. The direct memory access transfer method according to claim 11, wherein said step of setting said ratio includes the step of setting said bus access frequency of said direct memory access transfer, and

said step of counting said bus access frequency further includes the step of counting said bus access frequency of said direct memory access transfer in accordance with said set bus access frequency of said direct memory access transfer.

14. The direct memory access transfer method according to claim 13, wherein said step of controlling said bus access request includes the step of outputting the bus access request in such a way that said bus access frequency of direct memory access transfer to said bus access frequency of said another bus master is M:

N, where said set bus access frequency of said direct memory access transfer is a positive integer M and said set bus access frequency of said another bus master is a positive integer N.

15. The direct memory access transfer method according to claim 10, wherein said step of setting said ratio includes the steps of:

setting a weight of bus access by said direct memory access transfer, and

setting a weight of bus access by said another bus master, and said step of counting said bus access frequency includes the step of adding or subtracting said set weights of bus accesses by said direct memory access transfer and said bus master.

16. The direct memory access transfer method according to claim 15, wherein said step of adding or subtracting said set weights of bus accesses by said direct memory access transfer and said bus master includes the step of subtracting said set weight of said bus access by said direct memory access transfer every time said bus access by said direct memory access transfer is detected and adding said set weight of said bus access by said another bus master every time said bus access by said another bus master is detected, and

said step of controlling said bus access request asserts said bus access request when a weight of said bus access by said direct memory access transfer after said subtraction is at least 0, and negates said bus access request when a weight of said bus access by said direct memory access transfer after said subtraction has a negative value.

17. The direct memory access transfer method according to claim 10, wherein said step of controlling said bus access request includes the step of inputting bus freedom information indicating absence of a bus access request from another bus master and asserting said bus access request when said bus freedom information is asserted.

18. The direct memory access transfer method according to claim 10, wherein said step of setting said ratio includes the step of setting, for each of a plurality of channels, a ratio of bus access frequency of direct memory access transfer to bus access frequency of another bus master, and

said step of counting said bus access frequency includes the step of adding or subtracting values in accordance with bus access of a channel executing said direct memory access transfer of said plurality of channels and bus access of said another bus master.