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Second transfer logic causing a first transfer logic to check a data ready bit prior to each of multibit transfer of a continous transfer operation

  • US 6,691,183 B1
  • Filed: 05/18/1999
  • Issued: 02/10/2004
  • Est. Priority Date: 05/20/1998
  • Status: Expired due to Fees
First Claim
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1. A system for process control comprisinga processor, a field device, the field device, comprising any of a flowmeter, pressure sensor, temperature sensor, level sensor, valve, recorder, positioner, and other field device, an input/output module coupled to the processor and the field device, the input/output module comprising:

  • a first serial peripheral interface (SPI) in serial communication with a second SPI, the second SPI being coupled to the field device, first transfer logic section, coupled with the first SPI, that transfers a multi-bit datum between the processor and the field device via the first and second SPIs, second transfer logic section, coupled with the first transfer logic section, that effects a transfer transaction between the processor and the field device, the transfer transaction comprising transfer of a plurality of multi-bit datum relating to any of a common data access operation and a common data generation operation, the second transfer logic section effecting any of a continuous read data transfer operation and a continuous write data transfer operation by repeatedly performing steps of (i) invoking the first transfer logic section to transfer between the processor and the field device, via the first and second SPIs, one or more multi-bit commands for effecting an individual data transfer operation, and (ii) invoking the first transfer logic to transfer between the processor and the field device, via the first and second SPIs a multi-bit data comprising that individual data transfer, wherein the second transfer logic section causes the first logic section to check a “

    data ready”

    bit prior to each of multi-bit transfer that comprises said individual data transfer.

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