Efficient bus utilization in a multiprocessor system by dynamically mapping memory addresses
First Claim
1. An apparatus comprising:
- an arbiter to arbitrate access requests from N master processors via N master buses, the arbiter generating arbitration signals;
a mapping circuit to store mapping information to dynamically map an address space of P slave devices coupled to K slave buses based on the arbitration signals; and
a switching circuit coupled to the arbiter and the mapping circuit to connect the N master buses to K slave buses based on the arbitration signals and the mapping information.
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Abstract
In one embodiment of the present invention, a slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices from one of N master processors via a system bus controller and K slave buses. The K slave buses are configured to couple to the P slave devices. The system bus controller dynamically maps address spaces of the P slave devices. The slave bus decoder enables the one of the P slave devices to connect to one of the K slave buses when the one of the P slave devices is addressed by the one of the N master processors. The slave bus decoder is controlled by the system bus controller. In another embodiment of the present invention, the system bus controller includes an arbiter, a mapping circuit, and a switching circuit. The arbiter arbitrates access requests from N master processors via N master buses and generates arbitration signals. The mapping circuit stores mapping information to dynamically map an address space of K slave devices coupled to K slave buses based on the arbitration signals. The switching circuit connects the N master buses to K slave buses based on the arbitration signals and the mapping information.
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Citations
12 Claims
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1. An apparatus comprising:
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an arbiter to arbitrate access requests from N master processors via N master buses, the arbiter generating arbitration signals;
a mapping circuit to store mapping information to dynamically map an address space of P slave devices coupled to K slave buses based on the arbitration signals; and
a switching circuit coupled to the arbiter and the mapping circuit to connect the N master buses to K slave buses based on the arbitration signals and the mapping information. - View Dependent Claims (2, 3, 4)
a slave access decoder coupled to the arbiter and the N master processors to decode addresses issued by the N master processors, the slave access decoder generating control signals to P slave interface circuits, each of the P slave interface circuits being connected to each of the P slave devices.
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3. The apparatus of claim 1 wherein the mapping information is accessible to the N master processors.
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4. The apparatus of claim 2 wherein the mapping information is provided by a supervisor processor.
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5. An method comprising:
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arbitrating access requests from N master processors via N master buses by an arbiter, the arbiter generating arbitration signals;
storing mapping information in a mapping circuit to dynamically map an address space of P slave devices coupled to K slave buses based on the arbitration signals; and
connecting the N master buses to K slave buses based on the arbitration signals and the mapping information. - View Dependent Claims (6, 7, 8)
decoding addresses issued by the N master processors by a slave access decoder;
generating control signals to P slave interface circuits by the slave access decoder, each of the P slave interface circuits being connected to each of the P slave devices.
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7. The method of claim 5 wherein the mapping information is accessible to the N master processors.
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8. The method of claim 6 wherein the mapping information is provided by a supervisor processor.
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9. A system comprising:
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N bus masters having N master buses;
P slave devices coupled to K slave buses; and
A system bus controller coupled to the N bus masters and the K slave buses, the bus controller comprising;
an arbiter to arbitrate access requests from the N master processors via the N master buses, the arbiter generating arbitration signals, a mapping circuit to store mapping information to dynamically map an address space of P slave devices coupled to K slave buses based on the arbitration signals, and a switching circuit coupled to the arbiter and the mapping circuit to connect the N master buses to K slave buses based on the arbitration signals and the mapping information. - View Dependent Claims (10, 11, 12)
a slave access decoder coupled to the arbiter and the N master processors to decode addresses issued by the N master processors, the slave access decoder generating control signals to P slave interface circuits, each of the P slave interface circuits being connected to each of the P slave devices.
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11. The system of claim 9 wherein the mapping information is accessible to the N master processors.
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12. The system of claim 10 wherein the mapping information is provided by a supervisor processor.
Specification