Technique to test an integrated circuit using fewer pins

• US 6,691,267 B1
• Filed: 06/09/1998
• Issued: 02/10/2004
• Est. Priority Date: 06/10/1997
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wang, Bonnie, Sung, Chiakang, Huang, Joseph, Wang, Xiaobao, Nguyen, Khai
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/094,221
• Time in Patent Office: 2,072 Days
• Field of Search: 714/744, 714/725, 714/711, 714/719, 714/738, 714/718, 714/790, 714/701, 714/735, 710/72-75, 326/38-41, 326/16, 326/44, 365/200-201, 716/4
• US Class Current: 714/725
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G06F 11/2273 Test methods
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

A technique to implement functions requiring fewer pins of an integrated circuit to serially transfer data into the integrated circuit for multiple logic blocks. By reducing the required pins, this permits downbonding of the integrated circuit into a package with fewer pins. This technique may be used to implement test functions in a programmable logic device. Test data may be serially input using a test pin (310) for two or more columns (320) of logic blocks. The test data is stored in an A register (330), and may be later transferred into a B register (335).

Claims

1. A method of testing a programmable integrated circuit comprising:

transferring in serial via a test pin a frame of test bits to a first register, wherein the frame comprises bits for a plurality of columns of logic array blocks;

transferring in parallel the frame of test bits in the first register to a second register; and

using the frame of test bits from the second register to test a plurality of columns of logic array blocks.

2. The method of claim 1 wherein the transferring in serial is in response to a signal on a first clock line.

3. The method of claim 2 wherein the transferring in parallel is in response to a signal on a second clock line.

4. The method of claim 1 further comprising:

transferring in parallel the frame of test bits into FIFO chains within a plurality of columns of logic array blocks.

5. The method of claim 1 wherein the first register comprises:

a plurality of flip-flops arranged in a serial chain, wherein a first flip-flop in the serial chain is selectively coupled to the test pin.

6. The method of claim 1 wherein a first storage element of the first register is coupled to a second storage element of the first register and a first storage element of the second register.

7. The method of claim 6 wherein the first register may be preset using a first preset input and the second register may be preset using a second preset input.

8. The method of claim 1 wherein the first register comprises at least 32 bits.

9. The method of claim 6 wherein an output and an inverted output from the second register may be selectively passed to a logic array block.

10. A method of testing a programmable integrated circuit comprising:

clocking in test data into the programmable integrated circuit using a plurality of test pins wherein the test data input via a test pin is for a plurality of columns of logic blocks of the programmable integrated circuit;

storing the test data in a first register;

transferring the test data from the first register to a second register in parallel; and

testing the programmable integrated circuit storing the test data in a first register;

transferring the test data from the first register to a second register in parallel using the test data.

11. A method of testing a programmable integrated circuit as recited in claim 10 utilized to test a programmable integrated circuit that has been downbonded.

12. The method of claim 10 wherein at least 32 bits of test data are clocked in at each test pin.

13. The method of claim 10 further comprising:

transferring the test data input using a test pin to FIFO chains in a plurality of columns of logic blocks.

14. The method of claim 10 wherein each test pin is used to input data for two columns of logic blocks.

15. A method of testing an integrated circuit including an array of logic blocks arranged in rows and columns and an interconnect structure comprising a plurality of first conductors between columns of the logic blocks and a plurality of second conductors between the rows of the logic blocks, the method comprising:

serially receiving a frame of test bits with a test pin;

storing the frame of test bits using a first register, the first register selectively coupled to the test pin;

receiving in parallel the frame of test bits from the first register using a second register, the second register coupled to the first register; and

testing a plurality of columns of logic blocks with the frame of test bits from the second register.

16. The method of claim 15 further comprising:

while serially receiving the frame of test bits with the test pin, clocking the first register with a first clock signal on a first clock line.

17. The method of claim 16 further comprising:

while receiving in parallel the frame of test bits from the first register using a second register, clocking the second register with a second clock signal on a second clock line.

18. The method of claim 15 wherein the first register comprises:

a first clock line; and

a plurality of flip-flops arranged in a serial chain, wherein a first flip-flop in the serial chain is selectively coupled to the test pin.

19. The method of claim 18 wherein the first flip-flop in the first register is coupled to a second flip-flop in the first register and a first flip-flop in the second register.

20. The method of claim 19 wherein the first register comprises at least 32 flip-flops.

21. The method of claim 20 wherein the integrated circuit further comprises:

a multiplexer having a first input, a second input, and an output, wherein the first input is coupled to a output of the first flip-flop in the second register and the second input is coupled to an inverting output of the first flip-flop in the second register.

22. The method of claim 20 wherein the integrated circuit further comprises:

a multiplexer having a first input, a second input, and an output, wherein the first input is coupled to the test pin and the output is coupled to the first flip-flop in the first register.

23. A method of testing an integrated circuit including an array of logic blocks arranged in rows and columns and an interconnect structure comprising first conductors between columns of the logic blocks and second conductors between rows of the logic blocks, the method comprising:

receiving a plurality of signals external to the integrated circuit with a plurality of test pins, wherein the plurality of signals comprises test data; and

testing at least two columns of logic blocks with test data received by each test pin, wherein the integrated circuit further comprises;

a first register for two columns of logic blocks, wherein data is loaded into the first register via one test pin; and

a second register for two columns of logic blocks, wherein data stored in the first register is loaded into the second register in parallel.

24. The method of claim 23 wherein the integrated circuit further comprises:

a first plurality of flip flops coupled in a chain, wherein a first flip flop in the chain is selectably coupled to a test pin.

25. The method of claim 23 wherein the integrated circuit further comprises:

a first multiplexer coupled to selectively pass a first signal from a test pin or a second signal to a first multiplexer output;

a first flip flop coupled to the first multiplexer output;

a second flip flop, coupled to a first flip flop output; and

a second multiplexer, coupled to a second flip flop output, and a second multiplexer output coupled to a logic block.

26. The method of claim 25 wherein the first flip flop is further coupled to a first clock signal and the second flip flop is further coupled to a second clock signal.

27. The method of claim 25 wherein the second multiplexer is further coupled to a second flip flop inverted output.

28. A method of testing an integrated circuit comprising:

serially receiving a plurality of test bits using a test pin;

storing the plurality of test bits in a first register, the first register comprising a first flip-flop having an input selectively coupled to the test pin, and a second flip-flop having an input coupled to an output of the first flip-flop;

transferring in parallel the test bits from the first register to a second register, the second register comprising a third flip flop having an input coupled to the output of the first flip-flop in the first register; and

testing a plurality of columns of logic blocks using the test bits from the second register.

29. The method of claim 28 further comprising:

while serially receiving the plurality of test bits using the test pin, clocking the first register with a first clock signal on a first clock line.

30. The method of claim 29 further comprising:

while transferring in parallel the plurality of test bits from the first register to the second register, clocking the second register with a second clock signal on a second clock line.

31. A method of testing an integrated circuit including an array of logic blocks arranged in rows and columns and an interconnect structure comprising a plurality of first conductors between columns of the logic blocks and a plurality of second conductors between the rows of the logic blocks, the method comprising:

serially receiving a frame of test bits with a test pin;

storing the frame of test bits using a first register, the first register selectively coupled to the test pin;

receiving in parallel the frame of test bits from the first register using a second register, the second register coupled to the first register;

selectively providing each test bit or its complement in the frame of test bits to a column of logic blocks in a plurality of columns of logic blocks; and

testing the plurality of columns of logic blocks.

32. The method of claim 31 wherein the selectively proving each test bit or its complement is done using a multiplexer.

33. The method of claim 32 wherein the first register comprises a first plurality of flip-flops coupled in series, and the second register comprises a second plurality of flip-flops, each having an input coupled to an output of a flip-flop in the first plurality of flip-flops.