Error correction using packet combining during soft handover

• US 6,691,273 B2
• Filed: 01/17/2001
• Issued: 02/10/2004
• Est. Priority Date: 01/17/2001
• Status: Active Grant

• Current Assignee: Optis Wireless Technology, LLC (Brevet Capital)
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Wager, Stefan, Schön, Erik
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Dooley, Matthew C.
• Application Number:
  US09/764,506
• Publication Number:
  US 20020095635A1
• Time in Patent Office: 1,119 Days
• Field of Search: 714/748, 714/797, 714/807, 714/808, 714/751, 370/216, 370/241, 370/245, 370/260, 370/267, 370/268, 370/331, 370/332, 370/333
• US Class Current: 714/751
• CPC Class Codes: H04L 1/06 using space diversity
• CPC Class Codes: H04L 1/08 by repeating transmission, e.g. Verdan system H04L1/1858 and H04L1/189 take precedence
• CPC Class Codes: H04W 36/18 for allowing seamless reselection, e.g. soft reselection

Abstract

A method of error correction during a soft handover process is disclosed wherein a radio network control node receives a plurality of versions of the same data block. Two or more of the received versions of the data block are combined to determine a substantially error corrected version of the data block. The resulting substantially error corrected version of the data block may then be forwarded to to other network nodes.

Claims

1. A method of error correction during a soft handover process, comprising the steps of:

receiving at least two versions of a data block;

determining whether any of the received versions are error-free;

if a received version is error-free, outputting the error-free version of the data block;

if none of the received versions are error-free, selecting the best two versions according to guality information appended to each version;

performing an exclusive OR operation on a first version of the data block and a second version of the data block to identify potentially erroneous bit positions in the data block, said potentially erroneous bit positions having bit values that are not identical in the first and second versions of the data block;

successively inverting the bit values for the potentially erroneous bit positions in the data block to form all possible resulting combinations of bit values;

after each successive inverting of a bit value, performing an error detection determination for the resulting combination of bit values;

if the error detection determination indicates an error for the resulting combination of bit values, performing the error detection determination for a successive combination of bit values;

if the error detection determination indicates that the resulting combination of bit values is error-free, selecting the resulting combination of bit values as a substantially error corrected version of the data block; and

outputting the substantially error corrected version of the data block.

2. The method of claim 1, wherein the step of performing an error detecting determination comprises performing a cyclic redundancy check for each combination of bit values.

3. The method of claim 1, further comprising the steps of:

determining whether a predefined time period expires before an error-free combination of bit values is found; and

outputting the version of the data block having the best appended quality information if the predefined time period expires before an error-free combination of bit values is found.

4. A radio network control node, comprising:

input means for receiving at least two versions of a data block;

error detecting means for determining whether any of the received versions are error-free;

output means for outputting an error-free version of the data block;

packet combining logic responsive to a determination that none of the received versions are error-free, said packet combining logic being operable;

to select the best two versions of the data block according to quality information appended to each version;

to perform an exclusive OR operation on a first version and a second version of the data block to identify potentially erroneous bit positions in which bit values in the first and second versions of the data block are not identical;

to successively invert the bit values for the potentially erroneous bit positions in the data block to form all possible resulting combinations of bit values;

to perform an error detection determination for the resulting combination of bit values after each successive inverting of a bit value;

to perform the error detection determination for a successive combination of bit values if the error detection determination indicates an error for the resulting combination of bit values; and

to select the resulting combination of bit values as a substantially error corrected version of the data block if the error detection determination indicates that the resulting combination of bit values is error-free;

wherein, the output means is adapted to output the substantially error corrected version of the data block as determined by the packet combining logic.

5. The radio network control node of claim 4, wherein the error detection determination performed by the packet combining logic is a cyclic redundancy check that the packet combining logic performs for each combination of bit values.

6. The radio network control node of claim 4, wherein the packet combining logic is also operable to determine whether a predefined time period expires before an error-free combination of bit values is found, and the output means is also adapted to output the version of the data block having the best appended quality information if the packet combining logic indicates that the predefined time period expired before an error-free combination of bit values was found.