Exponential increments in FET size selection

• US 6,691,285 B1
• Filed: 08/27/2002
• Issued: 02/10/2004
• Est. Priority Date: 08/27/2002
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Anderson, Dave, Burden, David C.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Liu, Andrea
• Application Number:
  US10/229,535
• Time in Patent Office: 532 Days
• Field of Search: 716/4-10
• US Class Current: 716/119
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: G06F 30/373 Design optimisation

Abstract

A set of discrete transistor sizes spread in an exponential manner over a specified range is the basis for adjusted transistor sizes used to optimize a circuit. One of the discrete transistor sizes may be the original transistor size or other starting point for the optimization.

Claims

1. A method for choosing transistor sizes in a circuit optimization program, comprising:

selecting a discrete integer index wherein said integer index is selected from a range of integers from and including first value to and including a second value;

determining an adjusted transistor size from said integer index wherein a set of adjusted transistor sizes generated from a set of indexes ranging from said first value to said second value are approximately exponentially distributed from a first transistor size to a second transistor size.

2. The method of claim 1, wherein said first transistor size corresponds to said integer index having said first value and said second transistor size corresponds to said integer index having said second value.

3. The method of claim 1, wherein an initial integer index value corresponds to a starting transistor size and there are an equal number of integers from said first value to said initial integer index value and from said initial integer index value to said second value.

4. The method of claim 1 wherein there are a total of s integers between and including said first value and said second value and said set of adjusted transistor sizes are determined approximately from the formula $W=A·$

R(2

ns-1-1)

wherein W is the approximate adjusted transistor size, A is a starting transistor size, R is a range factor that determines said first transistor size and said second transistor size, and n is said integer index value.

5. The method of claim 4 wherein said set of adjusted transistor sizes is generated by rounding said formula to meet a set of design rules.

6. The method of claim 1 wherein said adjusted transistor size is a FET width to length ratio.

7. The method of claim 1 wherein said adjusted transistor size is a bipolar transistor area.

8. A method of optimizing a circuit, comprising:

adjusting a circuit parameter of a plurality of transistors;

choosing adjusted values for said circuit parameter from a plurality of sets of adjusted values wherein each of said sets of adjusted values are approximately exponentially distributed around a respective starting parameter value.

9. The method of claim 8 wherein said sets of adjusted values each range from a first value to a second value and there are an equal number of members of said set of adjusted values from said first value to said starting parameter value and from said starting parameter value to said second value.

10. The method of claim 8 wherein there are a total of s members of one of said sets of adjusted values and said one of said sets of adjusted values are determined approximately from the formula $W=A·$

R(2

ns-1-1)

wherein W is an approximate adjusted transistor size, A is said starting parameter value, R is a range factor that determines a smallest member of said one of said sets of adjusted values and a largest member of said one of said sets of adjusted values and n is an integer index value that is varied between zero and s−

1 to generate said one of said sets of adjusted values.

11. The method of claim 10 wherein said one of said sets of adjusted values is generated by rounding said formula to meet a set of design rules.

12. The method of claim 11 wherein said adjusted values represent FET width to length ratios.

13. The method of claim 11 wherein said adjusted values represent bipolar transistor areas.

14. A program storage medium readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for optimizing electronic circuits, said method steps comprising:

selecting a discrete integer index wherein said integer index is selected from a range of integers from and including first value to and including a second value;

determining an adjusted transistor size from said integer index wherein a set of adjusted transistor sizes generated from a set of indexes ranging from said first value to said second value are approximately exponentially distributed from a first transistor size to a second transistor size.

15. The program storage medium of claim 14, wherein said first transistor size corresponds to said integer index having said first value and said second transistor size corresponds to said integer index having said second value.

16. The program storage medium of claim 14, wherein an initial integer index value corresponds to a starting transistor size and there are an equal number of integers from said first value to said initial integer index value and from said initial integer index value to said second value.

17. The program storage medium of claim 14 wherein there are a total of s integers between and including said first value and said second value and said set of adjusted transistor sizes are determined approximately from the formula $W=A·$

R(2

ns-1-1)

wherein W is the approximate adjusted transistor size, A is a starting transistor size, R is a range factor that determines said first transistor size and said second transistor size, and n is said integer index value.

18. The program storage medium of claim 17 wherein said set of adjusted transistor sizes is generated by rounding said formula to meet a set of design rules.

19. The program storage medium of claim 14 wherein said adjusted transistor size is a FET width to length ratio.

20. The program storage medium of claim 14 wherein said adjusted transistor size is a bipolar transistor area.

21. A program storage medium readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for optimizing electronic circuits, said method steps comprising:

adjusting a circuit parameter of a transistor;

choosing adjusted values for said circuit parameter from a set of adjusted values wherein each of adjusted values are approximately exponentially distributed around a starting parameter value.

22. The program storage medium of claim 21 wherein said adjusted values range from a first value to a second value and there are an equal number of members of said set of adjusted values from said first value to said starting parameter value and from said starting parameter value to said second value.

23. The program storage medium of claim 21 wherein there are a total of s members of said set of adjusted values and said set of adjusted values are determined approximately from the formula $W=A·$

R(2

ns-1-1)

wherein W is an approximate adjusted transistor size, A is said starting parameter value, R is a range factor that determines a smallest member of said set of adjusted values and a largest member said set of adjusted values, and n is an integer index value that is varied between zero and s−

1.

24. The program storage medium of claim 23 wherein said one of said sets of adjusted values is generated by rounding said formula to meet a set of design rules.

25. The program storage medium of claim 21 wherein said adjusted values represent FET width to length ratios.

26. The program storage medium of claim 21 wherein said adjusted values represent bipolar transistor areas.