Exponential increments in FET size selection
First Claim
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1. A method for choosing transistor sizes in a circuit optimization program, comprising:
- selecting a discrete integer index wherein said integer index is selected from a range of integers from and including first value to and including a second value;
determining an adjusted transistor size from said integer index wherein a set of adjusted transistor sizes generated from a set of indexes ranging from said first value to said second value are approximately exponentially distributed from a first transistor size to a second transistor size.
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Abstract
A set of discrete transistor sizes spread in an exponential manner over a specified range is the basis for adjusted transistor sizes used to optimize a circuit. One of the discrete transistor sizes may be the original transistor size or other starting point for the optimization.
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Citations
26 Claims
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1. A method for choosing transistor sizes in a circuit optimization program, comprising:
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selecting a discrete integer index wherein said integer index is selected from a range of integers from and including first value to and including a second value;
determining an adjusted transistor size from said integer index wherein a set of adjusted transistor sizes generated from a set of indexes ranging from said first value to said second value are approximately exponentially distributed from a first transistor size to a second transistor size. - View Dependent Claims (2, 3, 4, 5, 6, 7)
wherein W is the approximate adjusted transistor size, A is a starting transistor size, R is a range factor that determines said first transistor size and said second transistor size, and n is said integer index value.
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5. The method of claim 4 wherein said set of adjusted transistor sizes is generated by rounding said formula to meet a set of design rules.
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6. The method of claim 1 wherein said adjusted transistor size is a FET width to length ratio.
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7. The method of claim 1 wherein said adjusted transistor size is a bipolar transistor area.
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8. A method of optimizing a circuit, comprising:
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adjusting a circuit parameter of a plurality of transistors;
choosing adjusted values for said circuit parameter from a plurality of sets of adjusted values wherein each of said sets of adjusted values are approximately exponentially distributed around a respective starting parameter value. - View Dependent Claims (9, 10, 11, 12, 13)
wherein W is an approximate adjusted transistor size, A is said starting parameter value, R is a range factor that determines a smallest member of said one of said sets of adjusted values and a largest member of said one of said sets of adjusted values and n is an integer index value that is varied between zero and s−
1 to generate said one of said sets of adjusted values.
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11. The method of claim 10 wherein said one of said sets of adjusted values is generated by rounding said formula to meet a set of design rules.
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12. The method of claim 11 wherein said adjusted values represent FET width to length ratios.
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13. The method of claim 11 wherein said adjusted values represent bipolar transistor areas.
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14. A program storage medium readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for optimizing electronic circuits, said method steps comprising:
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selecting a discrete integer index wherein said integer index is selected from a range of integers from and including first value to and including a second value;
determining an adjusted transistor size from said integer index wherein a set of adjusted transistor sizes generated from a set of indexes ranging from said first value to said second value are approximately exponentially distributed from a first transistor size to a second transistor size. - View Dependent Claims (15, 16, 17, 18, 19, 20)
wherein W is the approximate adjusted transistor size, A is a starting transistor size, R is a range factor that determines said first transistor size and said second transistor size, and n is said integer index value.
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18. The program storage medium of claim 17 wherein said set of adjusted transistor sizes is generated by rounding said formula to meet a set of design rules.
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19. The program storage medium of claim 14 wherein said adjusted transistor size is a FET width to length ratio.
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20. The program storage medium of claim 14 wherein said adjusted transistor size is a bipolar transistor area.
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21. A program storage medium readable by a computer, tangibly embodying a program of instructions executable by the computer to perform method steps for optimizing electronic circuits, said method steps comprising:
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adjusting a circuit parameter of a transistor;
choosing adjusted values for said circuit parameter from a set of adjusted values wherein each of adjusted values are approximately exponentially distributed around a starting parameter value. - View Dependent Claims (22, 23, 24, 25, 26)
wherein W is an approximate adjusted transistor size, A is said starting parameter value, R is a range factor that determines a smallest member of said set of adjusted values and a largest member said set of adjusted values, and n is an integer index value that is varied between zero and s−
1.
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24. The program storage medium of claim 23 wherein said one of said sets of adjusted values is generated by rounding said formula to meet a set of design rules.
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25. The program storage medium of claim 21 wherein said adjusted values represent FET width to length ratios.
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26. The program storage medium of claim 21 wherein said adjusted values represent bipolar transistor areas.
Specification