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Functional verification system

  • US 6,691,287 B2
  • Filed: 12/14/2000
  • Issued: 02/10/2004
  • Est. Priority Date: 12/14/2000
  • Status: Expired due to Term
First Claim
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1. A method of verifying the functionality of a target design representing an integrated circuit, said method comprising:

  • partitioning said target design into a plurality of combinatorial blocks;

    computing a truth table for each of said plurality of combinatorial block, wherein each truth table comprises a plurality of rows, with each row containing a plurality of inputs and a corresponding output bit;

    assigning each of said truth tables to one of a plurality of evaluation blocks;

    storing each of said truth tables in a random access storage device (RASD) associated with said evaluation block, wherein each output bit is stored at a location with a RASD address formed based on the corresponding plurality of inputs;

    evaluating a combinatorial block when the corresponding inputs are available to generate a corresponding output, wherein said evaluation is performed in a corresponding evaluation block to which said combinatorial block is assigned to, said evaluation being performed by accessing an associated RASD with an address formed by the corresponding available inputs; and

    storing said output generated by said evaluation locally in a plurality of evaluation blocks requiring said output for evaluation of additional combinatorial blocks, wherein each of said plurality of evaluation blocks includes a local storage element, and wherein the evaluation of said additional combinatorial blocks is simplified due to the local storage of said output.

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