Functional verification system

• US 6,691,287 B2
• Filed: 12/14/2000
• Issued: 02/10/2004
• Est. Priority Date: 12/14/2000
• Status: Expired due to Term

• Current Assignee: Synopsys Emulation and Verification SA (Synopsys Incorporated)
• Original Assignee: Tharas Systems, Inc. (Synopsys Incorporated)
• Inventors: Broukhis, Leonid Alexander, Narayanaswamy, Ramesh, Nixon, Ian Michael, Ganesan, Subbu
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US09/738,260
• Publication Number:
  US 20030041308A1
• Time in Patent Office: 1,153 Days
• Field of Search: 716/1-21, 324/756, 326/40, 710/269, 712/218, 714/724, 714/726, 714/735, 714/739
• US Class Current: 716/106
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Claims

1. A method of verifying the functionality of a target design representing an integrated circuit, said method comprising:

partitioning said target design into a plurality of combinatorial blocks;

computing a truth table for each of said plurality of combinatorial block, wherein each truth table comprises a plurality of rows, with each row containing a plurality of inputs and a corresponding output bit;

assigning each of said truth tables to one of a plurality of evaluation blocks;

storing each of said truth tables in a random access storage device (RASD) associated with said evaluation block, wherein each output bit is stored at a location with a RASD address formed based on the corresponding plurality of inputs;

evaluating a combinatorial block when the corresponding inputs are available to generate a corresponding output, wherein said evaluation is performed in a corresponding evaluation block to which said combinatorial block is assigned to, said evaluation being performed by accessing an associated RASD with an address formed by the corresponding available inputs; and

storing said output generated by said evaluation locally in a plurality of evaluation blocks requiring said output for evaluation of additional combinatorial blocks, wherein each of said plurality of evaluation blocks includes a local storage element, and

wherein the evaluation of said additional combinatorial blocks is simplified due to the local storage of said output.

2. The method of claim 1, further comprising transferring said output on a bus to said plurality of evaluation blocks, wherein each of said plurality of evaluation blocks can access said output by interfacing with said bus.

3. The method of claim 2, wherein said bus is designed to transfer a plurality of outputs, said method further comprising:

receiving said plurality of outputs in a plurality of multiplexors contained in each of said evaluation blocks;

selecting one of said outputs in each of said multiplexors; and

storing each of said selected outputs in a corresponding random access memory (RAM),

wherein said RAMs and said multiplexors are contained in said evaluation blocks.

4. The method of claim 3, further comprising sending a cluster number to said evaluation blocks, wherein said cluster number identifies a cluster containing a plurality of combinatorial blocks which are evaluated, wherein said selecting and said storing are performed according to said cluster number.

5. The method of claim 4, further comprising storing in each evaluation block an address associated with each cluster number, wherein said address indicates the specific location in each of said RAMs where the selected output is stored.

6. The method of claim 4, further comprising storing in each evaluation block a selection index associated with each cluster number for each of said multiplexors, wherein said selection in each multiplexor is performed according to said selection index.

7. The method of claim 3, further comprising sending a cluster number to said evaluation blocks, wherein said cluster number identifies a plurality of combinatorial blocks which are to be evaluated subsequently, wherein said cluster number determines the specific bits retrieved from each of said RAMs and used for subsequent evaluations.

8. The method of claim 7, further comprising storing in each evaluation block an address associated with each cluster number, wherein the address indicates the specific location in each of said RAMs from which a stored bit is to be retrieved.

9. The method of claim 8, further comprising storing in each evaluation block a selection index, and selecting one of the retrieved bits.

10. The method of claim 8, further comprising generating an address based on the retrieved bits and said cluster number, and retrieving data stored at a memory location as said address of said RASD, wherein the combinatorial blocks assigned to retrieved memory location are evaluated by the retrieval.

11. The method of claim 10, further comprising selecting a subset of the bits retrieved from said memory location on said bus, and sending only said subset of bits on said bus.

12. The method of claim 11, storing data indicative of the specific number of bits and the specific bits to be selected in case of each cluster, and selecting said subset based on the data indicative of the specific number of bits to be selected and the specific bits to be selected.

13. The method of claim 3, further comprising:

dividing said evaluation blocks into a plurality of groups;

generally sending a pre-specified outputs of evaluation blocks in each group to other evaluation blocks in the same group using a bus associated with each group; and

substituting some outputs of one group with outputs of another group in the bus corresponding to said one group such that the outputs of said another group can be made available to the evaluation blocks in said another group.

14. The method of claim 2, wherein said evaluation block comprises a combinatorial logic output evaluation (CLOE) containing a cross-connect and said RASD.

15. The method of claim 14, wherein said bus comprises 128 lines and wherein 16 CLOEs are used for verifying the functionality of said target design, said method comprising assigning 4 lines to each of said 16 CLOEs such that 4 output bits can be provided from each CLOE to the remaining 15 CLOEs.

16. The method of claim 1, further comprising providing a feedback path within an evaluation block performing said evaluation such that said output can be used immediately in the same evaluation block without having to store said output.

17. A method of verifying the functionality of a target design representing an integrated circuit, said method comprising:

partitioning said target design into a plurality of combinatorial blocks;

computing a truth table for each of said plurality of combinatorial block, wherein each truth table comprises a plurality of rows, with each row containing a plurality of inputs and a corresponding output bit;

assigning each of said truth tables to one of a plurality of evaluation blocks;

storing each of said truth tables in a random access storage device (RASD) associated with said evaluation block, wherein each output bit is stored at a location with a RASD address formed based on the corresponding plurality of inputs;

evaluating a combinatorial block when the corresponding inputs are available to generate a corresponding output, wherein said evaluation is performed in a corresponding evaluation block to which said combinatorial block is assigned to, said evaluation being performed by accessing an associated RASD with an address formed by the corresponding available inputs; and

transferring said output on a bus to said plurality of evaluation blocks, wherein each of said plurality of evaluation blocks can access said output by interfacing with said bus.

18. A functional verification system to verify the functionality of a target design representing an integrated circuit, said functional verification system comprising:

partitioning means for partitioning said target design into a plurality of combinatorial blocks;

computing means for computing a truth table for each of said plurality of combinatorial block, wherein each truth table comprises a plurality of rows, with each row containing a plurality of inputs and a corresponding output bit;

assignment means for assigning each of said truth tables to one of a plurality of evaluation blocks;

random access storage means for storing each of said truth tables associated with said evaluation block, wherein each output bit is stored at a location with a RASD address formed based on the corresponding plurality of inputs;

evaluation means for evaluating a combinatorial block when the corresponding inputs are available to generate a corresponding output, wherein said evaluation is performed in a corresponding evaluation block to which said combinatorial block is assigned to, said evaluation being performed by accessing an associated RASD with an address formed by the corresponding available inputs; and

memory means for storing said output generated by said evaluation locally in a plurality of evaluation blocks requiring said output for evaluation of additional combinatorial blocks, wherein each of said plurality of evaluation blocks includes a local storage element, and

wherein the evaluation of said additional combinatorial blocks is simplified du to the local storage of said output.

19. A functional verification system to verify the functionality of a target design representing an integrated circuit, said functional verification system comprising:

a random access storage device (RASD) to store the outputs corresponding to a plurality of rows of a plurality of truth tables, each row of the truth table representing an input combination to a combinatorial block, wherein the combinatorial blocks associated with the truth tables are assigned to said RASD, wherein the combinatorial blocks are generated by partitioning said target design, each output being stored at a location having an address formed based on the corresponding input combination;

a cross-connect (XCON) coupled to said RASD, said XCON to generate said address when the corresponding inputs are available, said XCON retrieving the outputs stored in the location at said address;

a run time controller to receive said outputs from said XCON and to make the outputs available on a bus to a plurality of XCONs including said XCON,

wherein said plurality of XCONs can access the outputs by interfacing with said bus and evaluate combinatorial blocks assigned to the respective RASDs.

20. The functional verification system of claim 19, wherein said RASD and said XCON are contained in a combination logic output evaluation (CLOE) block.

21. The functional verification system of claim 20, further comprising a plurality of verification boards and a backplane, wherein said CLOE is contained in a verification board and said backplane allows said CLOE to communicate with other CLOEs.

22. The functional verification system of claim 19, wherein said XCON comprises a plurality of muxkongs, with each muxkong being designed to store the specific bits of the outputs received on said bus in one order, and to provide the bits as address bits to said RASD in a different order.

23. The functional verification system of claim 22, wherein each muxkong comprises:

a first plurality of multiplexors to receive outputs received on said bus, each of said first plurality of multiplexors selecting one of said outputs received on said bus;

a plurality of random access memories (RAMs), with each RAM being connected to one of said first plurality of multiplexors, each RAM storing the corresponding selected output.

24. The functional verification system of claim 23, wherein each muxkong further comprises:

a first stack to store a start address and a count associated with each of a plurality of clusters, wherein each cluster identifies a plurality of combinatorial blocks;

a write controller coupled to said first stack, said write controller receiving a cluster identifier from said run time controller and determining a start address and count for the cluster identified by said cluster identifier, wherein said write controller causes a number of said first plurality of multiplexers equal to said count for the identified cluster to select a bit from the outputs received on said bus.

25. The functional verification system of claim 24, further comprising a second stack associated with one of said first plurality of multiplexors, wherein said second stack stores a selection index associated with each RAM address, wherein said selection index is used to control said one of said first plurality of multiplexors to select a desired bit for storing in the corresponding RAM, wherein said desired bit is provided by said muxkong for a subsequent evaluation.

26. The functional verification system of claim 23, said muxkong further comprising:

a read controller coupled to said plurality of RAMs, wherein said read controller receives a cluster number identifying a cluster, wherein each cluster contains a plurality of combinatorial blocks, said read controller identifying a specific bit to be retrieved from each of said RAMs; and

a multiplexor coupled to said read controller and said RAMs, said multiplexor selecting one of the outputs of said RAMs under the control of said read controller.

27. The functional verification system of claim 26, further comprising an evaluation control unit, wherein said evaluation control unit receives said cluster number and said bit selected by said multiplexor in each muxkong, wherein said evaluation control unit generates a RASD address based on said cluster number and said bits selected by said multiplexor in each muxkong, wherein a location in said RASD with said RASD address represents the outputs of the combinatorial blocks in said cluster identified by said cluster number.

28. The functional verification system of claim 26, wherein said evaluation control unit selects a subset of the bits retrieved from said location in said RASD, and sends the subset of said bits on said bus.

29. The functional verification system of claim 28, wherein said evaluation control unit receives a 32 bit word from said RASD and selects up to 4 bits from said 32 bit word.

30. The functional verification system of claim 20, wherein a plurality of CLOEs are grouped into a plurality of groups with each group receiving outputs of evaluation on a corresponding bus, said functional verification system further comprising a swapper coupled to each of said bus and the outputs of said plurality of CLOEs forming said groups, said swapper being designed to provide the outputs of group of CLOEs to another group of CLOEs using the bus corresponding to said another group of CLOEs.

31. The functional verification system of claim 20, wherein said XCON is configured by an external combination logic output generator (CLOG), which partitions said target design into plurality of combinatorial blocks.

32. A functional verification system to verify the functionality of a target design representing an integrated circuit, said functional verification system comprising:

partitioning means for partitioning said target design into a plurality of combinatorial blocks;

computing means for computing a truth table for each of said plurality of combinatorial block, wherein each truth table comprises a plurality of rows, with each row containing a plurality of inputs and a corresponding output bit;

assignment means for assigning each of said truth tables to one of a plurality of evaluation blocks;

random access storage means for storing each of said truth tables associated with said evaluation block, wherein each output bit is stored at a location with a RASD address formed based on the corresponding plurality of inputs;

evaluation means for evaluating a combinatorial block when the corresponding inputs are available to generate a corresponding output, wherein said evaluation is performed in a corresponding evaluation block to which said combinatorial block is assigned to, said evaluation being performed by accessing an associated RASD with an address formed by the corresponding available inputs; and

transferring means for transferring said output on a bus to said plurality of evaluation blocks, wherein each of said plurality of evaluation blocks can access said output by interfacing with said bus.