Thin film transistors with dual layered source/drain electrodes and manufacturing method thereof, and active matrix display device and manufacturing method thereof

• US 6,692,997 B2
• Filed: 02/20/2002
• Issued: 02/17/2004
• Est. Priority Date: 03/02/2001
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung SDI Company Limited
• Inventors: Park, Sang Il, Yoo, Kyung Jin, So, Woo Young
• Primary Examiner(s): Eckert, George
• Assistant Examiner(s): RICHARDS, NORMAN DREW
• Application Number:
  US10/077,771
• Publication Number:
  US 20020125477A1
• Time in Patent Office: 727 Days
• Field of Search: 438/149, 438/151, 438/163, 438/164, 438/303, 438/609, 438/652, 438/656, 438/688
• US Class Current: 438/151
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

The present invention discloses a method of manufacturing an active matrix display device, comprising: a) forming a semiconductor layer on an insulating substrate; b) forming a gate insulating layer over the whole surface of the substrate while convering the semiconductor layer; c) forming a gate electrode on the gate insulating layer over the semiconductor layer; d) forming spacers on both side wall portions of the gate electrode while exposing both end portions of the semiconductor layer; e) ion-implaing a high-density impurity into the semiconductor layer to form high-density source and drain regions in the semiconductor layer; f) depositing sequentially a transparent conductive layer and a metal layer on the inter insulating layer; g) patterning the transparent conductive layer and the metal layer to form the source and drain electrodes, the source and drain electrodes directly contacting the high-density source and drain regions and having a dual-layered structure; h) forming a passivation layer over the whole surface of the substrate; i) etching the passivation layer and the metal layer to form an opening portion exposing a portions of the transparent conductive layer, thereby forming a pixel electrode; and j) performing a reflow process to cover the metal layer in the opening portion by the passivation layer.

Claims

1. A method of manufacturing an active matrix display device, comprising:

a) forming a semiconductor layer on an insulating substrate;

b) forming a gate insulating layer over the whole surface of the substrate while covering the semiconductor layer;

c) forming a gate electrode on the gate insulating layer over the semiconductor layer;

d) ion-implanting a high-density impurity into the semiconductor layer to form high-density source and drain regions in the semiconductor layer;

e) forming an inter insulating layer over the whole surface of the substrate;

f) etching the inter insulating layer to form contact holes, the contact holes exposing portions of the high-density source and drain regions;

g) depositing sequentially a transparent conductive layer and a metal layer on the inter insulating layer;

h) patterning the transparent conductive layer and the metal layer to form the source and drain electrodes, the source and drain electrodes contacting the high-density source and drain regions through the contact holes and having a dual-layered structure;

i) forming a passivation layer over the whole surface of the substrate;

j) etching the passivation layer and the metal layer to form an opening portion exposing a portion of the transparent conductive layer, thereby forming a pixel electrode; and

k) performing a reflow process to cover the metal layer in the opening portion by the passivation layer.

2. The method of claim 1, wherein the metal layer is made of a meterial having a lower specific resistance than the transparent conductive layer;

and wherein the metal layer is made of one of Al, Al-alloy, Mo, Mo-alloy, Cr, and Ti and the transparent conductive layer is made of one of indium tin oxide, indium zinc oxide, tin oxide and indium oxide.

3. The method of claim 1, wherein non-ion-implanted portions of the semiconductor layer under the spacers serve as off-set regions, whereby the source and drains regions have an off-set structure.

4. The method of claim 1, further comprising, ion-implanting a low-density impurity having the same conductivity as the high-density source and drain regions into portions of the semiconductor layer directly under the spacers to form low-density source and drain regions after the gate formation step, whereby the source and drain regions have an LDD structure.

5. A method of manufacturing an active matrix display device having an opening portion, comprising:

a) forming a semiconductor layer on an insulating substrate;

b) forming a gate insulating layer over the whole surface of the substrate while covering the semiconductor layer;

c) forming a gate electrode on the gate insulating layer over the semiconductor layer;

d) ion-implanting a high-density impurity into the exposed portions of the semiconductor layers to form high-density source and drain regions;

e) forming an inter insulating layer over the whole surface of the substrate;

f) etching the inter insulating layer including to form contact holes exposing portions of the high-density source and drain regions;

g) depositing sequentially a transparent conductive layer and a metal layer over the whole surface of the substrate;

h) coating a photoresist layer over the whole surface of the substrate;

i) patterning the photoresist layer using a half-tone mask to from a photoresist pattern, the photoresist pattern exposing a portion of the metal layer over the gate electrode and including a relative thin portion having a thickness thinner than the rest portion thereof at a loation thereof corresponding to the opening portion;

j) patterning the transparent conductive layer and the metal layer using the photoresist pattern as a mask to form source and drain electrodes and to expose a portion of the transparent conductive layer corresponding to the opening portion, the source and drain electrodes respectively contacting the high-density source and drain regions through the contact holes and having a dual-layered structure; and

k) depositing a passivation layer over the whole surface of the substrate and etching the passivation layer to form the opening portion, thereby forming a pixel electrode.

6. The method of claim 5, wherein the metal layer is made of a meterial having a lower specific resistance than the transparent conductive layer;

and wherein the metal layer is made of one of Al, Al-alloy, Mo, Mo-alloy, Cr, and Ti and the transparent conductive layer is made of one of indium tin oxide, indium zinc oxide, tin oxide and indium oxide.

7. The method of claim 5, wherein non-ion-implanted portions of the semiconductor layer under the spacers serve as off-set regions, whereby the source and drains regions have an off-set structure.

8. The method of claim 5, further comprising, ion-implanting a low-density impurity having the same conductivity as the high-density source and drain regions into portions of the semiconductor layer directly under the spacers to form low-density source and drain regions after the gate formation step, whereby the source and drain regions have an LDD structure.

9. A method of manufacturing an active matrix display device, comprising:

a) forming a semiconductor layer on an insulating substrate;

b) forming a gate insulating layer over the whole surface of the substrate while covering the semiconductor layer;

c) forming a gate electrode on the gate insulating layer over the semiconductor layer;

d) forming spacers on both side wall portions of the gate electrode while exposing both end portions of the semiconductor layer;

e) ion-implanting a high-density impurity into the semiconductor layer to form high-density source and drain regions in the semiconductor layer;

f) depositing sequentially a transparent conductive layer and a metal layer on;

g) patterning the transparent conductive layer and the metal layer to form the source and drain electrodes, the source and drain electrodes directly contacting the high-density source and drain regions and having a dual-layered structure;

h) forming a passivation layer over the whole surface of the substrate;

i) etching the passivation layer and the metal layer to form an opening portion exposing a portion of the transparent conductive layer, thereby forming a pixel electrode; and

j) performing a reflow process to cover the metal layer in the opening portion by the passivation layer.

10. The method of claim 9, wherein the metal layer is made of a meterial having a lower specific resistance than the transparent conductive layer;

and wherein the metal layer is made of one of Al, Al-alloy, Mo, Mo-alloy, Cr, and Ti and the transparent conductive layer is made of one of indium tin oxide, indium zinc oxide, tin oxide and indium oxide.

11. The method of claim 9, wherein non-ion-implanted portions of the semiconductor layer under the spacers serve as off-set regions, whereby the source and drains regions have an off-set structure.

12. The method of claim 9, further comprising, ion-implanting a low-density impurity having the same conductivity as the high-density source and drain regions into portions of the semiconductor layer directly under the spacers to form low-density source and drain regions after the gate formation step, whereby the source and drain regions have an LDD structure.

13. A method of manufacturing an active matrix display device having an opening portion, comprising:

a) forming a semiconductor layer on an insulating substrate;

b) forming a gate insulating layer over the whole surface of the substrate while covering the semiconductor layer;

c) forming a gate electrode on the gate insulating layer over the semiconductor layer;

d) forming spacers on both side wall portions of the gate electrode while exposing both end portions of the semiconductor layer;

e) ion-implanting a high-density impurity into the exposed portions of the semiconductor layer to form high-density source and drain regions;

f) depositing sequentially a transparent conductive layer and a metal layer over the whole surface of the substrate;

g) coating a photoresist layer over the whole surface of the substrate;

h) patterning the photoresist layer using a half-tone mask to from a photoresist pattern, the photoresist pattern exposing a portion of the metal layer over the gate electrode and including a relative thin portion having a thickness thinner than the rest portion thereof at a loation thereof corresponding to the opening portion;

i) patterning the transparent conductive layer and the metal layer using the photoresist pattern as a mask to form source and drain electrodes and to expose a portion of the transparent conductive layer corresponding to the opening portion, the source and drain electrodes respectively contacting the high-density source and drain regions through the contact holes and having a dual-layered structure; and

j) depositing a passivation layer over the whole surface of the substrate and etching the passivation layer to form the opening portion, thereby forming a pixel electrode.

14. The method of claim 13, wherein the metal layer is made of a meterial having a lower specific resistance than the transparent conductive layer;

and wherein the metal layer is made of one of Al, Al-alloy, Mo, Mo-alloy, Cr, and Ti, and the transparent conductive layer is made of one of indium tin oxide, indium zinc oxide, tin oxide and indium oxide.

15. The method of claim 13, wherein non-ion-implanted portions of the semiconductor layer under the spacers serve as off-set regions, whereby the source and drains regions have an off-set structure.

16. The method of claim 13, further comprising, ion-implanting a low-density impurity having the same conductivity as the high-density source and drain regions into portions of the semiconductor layer directly under the spacers to form low-density source and drain regions after the gate formation step, whereby the source and drain regions have an LDD structure.