Method for improved processing and etchback of a container capacitor

• US 6,693,015 B2
• Filed: 08/14/2001
• Issued: 02/17/2004
• Est. Priority Date: 01/25/1999
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Micron Technology, Inc.
• Inventors: Carstensen, Robert K.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): YEVSIKOV, VICTOR V
• Application Number:
  US09/928,308
• Publication Number:
  US 20020000596A1
• Time in Patent Office: 917 Days
• Field of Search: 257/296, 257/301, 257/303, 257/306-310, 257/532, 438/396, 438/239, 438/242, 438/253, 438/387
• US Class Current: 438/306
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug

Abstract

A capacitor having improved size for enhanced capacitance and a method of forming the same are disclosed. In one embodiment, the capacitor is a stacked container capacitor used in a dynamic random access memory circuit. The capacitor provides a capacitor that has high storage capacitance which provides an increased efficiency for a cell without an increase in the size of the cell.

Claims

1. An integrated circuit capacitor comprising:

a first electrode and a second electrode formed on a substrate; and

a dielectric provided between said electrodes, said capacitor having a lower section formed in a first insulating layer and an upper section formed in a second insulating layer, said lower section being formed beneath said upper section, said upper section having a width greater than said lower section, wherein said first electrode has at least a portion which is both disposed over and in contact with said first insulating layer, wherein a portion of a third insulating layer is in contact with two opposing surfaces of said second electrode in said lower section, and wherein the third insulating layer is in contact with two opposing surfaces of said second electrode in said upper section.

2. The integrated circuit capacitor according to claim 1, wherein said capacitor is a container capacitor.

3. The integrated circuit capacitor according to claim 1, wherein said first electrode and second electrode are independently formed of a material selected from doped polysilicon, hemispherical grained polysilicon or a metal.

4. The integrated Circuit capacitor according to claim 3, wherein said first electrode is formed of hemispherical grained polysilicon.

5. The integrated circuit capacitor according to claim 3, wherein said second electrode is formed of doped polysilicon.

6. The integrated circuit capacitor according to claim 1, wherein said dielectric is selected from the group consisting of oxides and nitrides.

7. The integrated circuit capacitor according to claim 6, wherein said dielectric is an oxide selected from the group consisting of Ta₂O₅, SrTiO₃, Y₂O₃, Nb₂O₅, ZrO₂ titanium oxide, and silicon nitride.

8. The integrated circuit capacitor according to claim 1, wherein said capacitor is a stacked capacitor.

9. The integrated circuit capacitor according to claim 1, wherein said first electrode is in direct contact with an active area of said substrate.

10. The integrated circuit capacitor according to claim 1, wherein said capacitor is part of a DRAM cell.

11. A computer system comprising:

a processor; and

a memory circuit connected to the processor, wherein at least one of said processor and memory circuit contains at least one capacitor formed on a substrate having a first electrode and a second electrode with a dielectric layer provided between said electrodes, said capacitor having a lower section formed in a first insulating layer and an upper section formed in a second insulating layer, said lower section being formed beneath said upper section, said upper section having a width greater than said lower section, wherein said first electrode has at least a portion which is both disposed over and in contact with said first insulating layer, wherein said first electrode has a lower portion which is in contact with insulating spacers, said insulating spacers being a different material than said first insulating layer.

12. The computer system according to claim 11, wherein said capacitor is a container capacitor.

13. The computer system according to claim 11, wherein said first electrode and second electrode are independently formed of a material selected from doped polysilicon, hemispherical grained polysilicon or a metal.

14. The computer system according to claim 13, wherein said first electrode is formed of hemispherical grained polysilicon.

15. The computer system according to claim 13, wherein said second electrode is formed of doped polysilicon.

16. The computer system according to claim 11, wherein said dielectric is selected from the group consisting of oxides and nitrides.

17. The computer system according to claim 16, wherein said dielectric is an oxide selected from the group consisting of Ta₂O₅, SrTiO₃, Y₂₀₃, Nb₂O₅, ZrO₂ titanium oxide, and silicon nitride.

18. The computer system according to claim 11, wherein said capacitor is a stacked capacitor.

19. The computer system according to claim 11, wherein said first electrode is in direct contact with an active area of said substrate.

20. The computer system of claim 11, wherein said memory circuit is a DRAM memory circuit.

21. A memory cell comprising:

a transistor; and

a capacitor formed on a substrate having a first electrode and a second electrode with a dielectric layer provided between said electrodes, said transistor and capacitor being connected in a memory array, said capacitor having a lower section formed in a planar first insulating layer and an upper section formed in a second insulating layer, said lower section being formed beneath said upper section, said upper section having a width greater than said lower section, and wherein said first electrode has at least a portion which is both disposed over and in contact with said first insulating layer.

22. The memory cell according to claim 21, wherein said capacitor is a container capacitor.

23. The memory cell according to claim 21, wherein said first electrode and second electrode are independently formed of a material selected from doped polysilicon, hemispherical grained polysilicon or a metal.

24. The memory cell according to claim 23, wherein said first electrode is formed of hemispherical grained polysilicon.

25. The memory cell according to claim 23, wherein said second electrode is formed of doped polysilicon.

26. The memory cell according to claim 21, wherein said dielectric is selected from the group consisting of oxides and nitrides.

27. The memory cell according to claim 21, wherein said capacitor is a stacked capacitor.

28. The memory cell according to claim 21, wherein said first electrode is in direct contact with an active area of said substrate.

29. The memory cell according to claim 21, wherein said integrated circuit is a DRAM cell.

30. A DRAM cell having a container capacitor, said capacitor comprising:

a first electrode and a second electrode formed on a substrate; and

a dielectric provided between said electrodes, said capacitor having a lower section formed in a first insulating layer and an upper section formed in a second insulating layer, said lower section being formed beneath said upper section, said upper section having a width greater than said lower section, wherein said first electrode has at least a portion which is both disposed over and in contact with said first insulating layer, wherein a portion of a third insulating layer is in contact with two opposing surfaces of said second electrode in said lower section, and wherein a portion of said third insulating layer is in contact with two opposing surfaces of said second electrode in said upper section.

31. The DRAM cell according to claim 30, wherein said capacitor is a container capacitor.

32. The DRAM cell according to claim 30, wherein said first electrode and second electrode are independently formed of a material selected from doped polysilicon, hemispherical grained polysilicon or a metal.

33. The DRAM cell according to claim 32, wherein said first electrode is formed of hemispherical grained polysilicon.

34. The DRAM cell according to claim 32, wherein said second electrode is formed of doped polysilicon.

35. The DRAM cell according to claim 30, wherein said dielectric is selected from the group consisting of oxides and nitrides.

36. The DRAM cell according to claim 30, wherein said capacitor is a stacked capacitor.

37. The DRAM cell according to claim 30, wherein said first electrode is in direct contact with an active area of said substrate.

38. The DRAM cell according to claim 30, wherein said integrated circuit is a DRAM cell.