Semiconductor component with a semiconductor body having a multiplicity of pores and method for fabricating

• US 6,693,024 B2
• Filed: 06/10/2002
• Issued: 02/17/2004
• Est. Priority Date: 06/08/2001
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Lehmann, Volker, Schubert, Axel
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/165,936
• Publication Number:
  US 20020197832A1
• Time in Patent Office: 617 Days
• Field of Search: 438/409, 438/542, 438/667, 438/675, 438/684, 438/960, 438/212, 438/268, 438/273, 257/1, 257/3, 257/4, 257/302, 257/774
• US Class Current: 438/542
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/868 PIN diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 31/022408 for devices characterised by at least one potential jump barrier or surface barrier
• CPC Class Codes: Y10S 438/96 Porous semiconductor

Abstract

The semiconductor component is fabricated on the basis of a semiconductor body with a first and a second surface. A multiplicity of pores are formed in the semiconductor body. The pores extend into the semiconductor body proceeding from the first surface and ending below the second surface. The electrical conductivity of the semiconductor body, that is of the component, is increased in the region of the pores. The corresponding semiconductor component has connection contacts on the first and second surfaces.

Claims

1. A method of fabricating a vertical semiconductor component, which comprises the following steps:

providing a semiconductor body with a first and a second surface;

fabricating a multiplicity of pores in the semiconductor body, the pores proceeding from the first surface, extending into the semiconductor body, and ending within the semiconductor body;

increasing an electrical conductivity of the semiconductor body in the region of the pores for producing a low ohmic connection zone including the pores and the semiconductor material surrounding the pores; and

producing active regions with pn-junctions in a region not permeated by the pores and adjacent the second surface, the active regions to be contacted by the first surface over the low ohmic connection zone.

2. The method according to claim 1, which comprises doping regions of the semiconductor body that are uncovered in the pores.

3. The method according to claim 2, which comprises carrying out a diffusion step following the doping step.

4. The method according to claim 1, which comprises at least partly filling the pores with an electrically conductive material.

5. The method according to claim 1, which comprises at least partly filling the pores with a material selected from the group consisting of metal and polysilicon.

6. The method according to claim 1, wherein the semiconductor body has a given thickness and the pores are fabricated to extend into the semiconductor body to a depth of between 50% and 95% of the given thickness of the semiconductor body.

7. A vertical semiconductor component, comprising:

a semiconductor body having a first surface and a second surface each having connection contacts;

a multiplicity of pores formed in said semiconductor body, said pores extending into said semiconductor body, proceeding from said first surface and ending within said semiconductor body; and

semiconductor material surrounding said pores, said semiconductor material surrounding said pores having an electrical conductivity being increased to form a low ohmic connection zone including said pores and said semiconductor material surrounding said pores; and

active regions with pn-junctions, said active regions formed in a region not permeated by the pores and adjacent the second surface, said active regions to be contacted by said first surface over said low ohmic connection zone.

8. The semiconductor component according to claim 7, wherein said semiconductor body is doped at sidewalls of said pores.

9. The semiconductor component according to claim 7, which comprises an electrically conductive material at least partly filling said pores.

10. The semiconductor component according to claim 9, wherein said electrically conductive material is a material selected from the group consisting of metal and polysilicon.

11. The semiconductor component according to claim 7, wherein said semiconductor body has a given thickness and said pores extend into said semiconductor body to a depth of between 50% and 95% of said given thickness of said semiconductor body.