Junction field-effect transistor with more highly doped connecting region

• US 6,693,314 B2
• Filed: 06/22/2001
• Issued: 02/17/2004
• Est. Priority Date: 12/22/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: SiCED Electronics Development GmbH & Co. KG (Siemens AG)
• Inventors: Tihanyi, Jenoe, Stephani, Dietrich, Mitlehner, Heinz
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Soward, Ida M.
• Application Number:
  US09/888,037
• Publication Number:
  US 20020014640A1
• Time in Patent Office: 970 Days
• Field of Search: 257/256, 257/263, 257/287, 257/192, 257/273, 257/270
• US Class Current: 257/256
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.

Claims

1. A junction field-effect transistor, comprising:

a semiconductor region having a first surface and a second surface opposite said first surface, said semiconductor region including;

a drain contact region disposed at said first surface of said semiconductor region and formed of a first conductivity type;

an inner region disposed above said drain contact region and formed of said first conductivity type; and

a control region disposed above said inner region and formed of a second conductivity type;

a gate electrode disposed above said control region;

a source contact region formed of said first conductivity type, said control region and said inner region being at least partly disposed between said source contact region and said drain contact region;

a first connection region formed of said first conductivity type, said first connection region having at least one inner part running within said semiconductor region substantially perpendicularly to said first surface, said first connection region directly connected to said source contact region in a low-impedance manner and being doped more highly than said inner region forming a current path between said source contact region and said drain contact region having lower losses in a forward-biasing situation than for a current flow via said inner region; and

a second connection region formed of said second conductivity type and having at least one inner part running within said semiconductor region substantially perpendicularly to said first surface, said second connection region compensating for an influence of said first connection region in a reverse-biasing situation.

2. The junction field-effect transistor according to claim 1, wherein said semiconductor region has a recess formed therein, said recess extending from said second surface of said semiconductor region into said semiconductor region and within said recess said inner part of said first connection region and said inner part of said second connection region are disposed and run perpendicularly to said first surface.

3. The junction field-effect transistor according to claim 2, where said inner part of said first connection region adjoins edges of said recess.

4. The junction field-effect transistor according to claim 1, wherein said inner part of said first connection region runs perpendicularly to said first surface and is assigned said inner part of said second connection region and runs parallel to said inner part of said second connection region.

5. The junction field-effect transistor according to claim 4, wherein said inner part of said first connection region directly adjoins said inner part of said second connection region.

6. The junction field-effect transistor according to claim 1, wherein said first connection region extends as far as said drain contact region.

7. The junction field-effect transistor according to claim 1, wherein said inner part of said first connection region has a doping concentration which at least largely corresponds to a breakdown charge.

8. The junction field-effect transistor according to claim 1, wherein said inner part of said second connection region has doping concentration identical to said inner part of said first connection region.

9. The junction field-effect transistor according to claim 1, wherein said semiconductor region, said first connection region, said second connection region and said source contact region are composed of silicon carbide.

10. The junction field-effect transistor according to claim 9, wherein said inner part of said first connection region has a doping concentration of at most 1·

10¹⁸ cm<sup>−

3</sup>.

11. The junction field-effect transistor according to claim 1, wherein said semiconductor region, said first connection region, said second connection region, and said source contact region are composed of silicon.

12. The junction field-effect transistor according to claim 1, wherein said control region extends along said second surface of said semiconductor region.

13. The junction field-effect transistor according to claim 1, wherein said gate electrode makes ohmic contact with said control region and said second connection region.

14. The junction field-effect transistor according to claim 1, wherein said first connection region has an outer part disposed on said semiconductor region above said control region and said source contact region is disposed on said outer part of said first connection region, and said second connection region has an outer part partly covering said source contact region, with a result that, in an event of a projection perpendicular to said first surface, a projection of said control region and a projection of said outer part of said second connection region overlap.

15. The junction field-effect transistor according to claim 1, wherein said connection region runs parallel to said first surface except for said at least one inner part which runs within said semiconductor region substantially perpendicularly to said first surface.