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Junction field-effect transistor with more highly doped connecting region

  • US 6,693,314 B2
  • Filed: 06/22/2001
  • Issued: 02/17/2004
  • Est. Priority Date: 12/22/1998
  • Status: Expired due to Term
First Claim
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1. A junction field-effect transistor, comprising:

  • a semiconductor region having a first surface and a second surface opposite said first surface, said semiconductor region including;

    a drain contact region disposed at said first surface of said semiconductor region and formed of a first conductivity type;

    an inner region disposed above said drain contact region and formed of said first conductivity type; and

    a control region disposed above said inner region and formed of a second conductivity type;

    a gate electrode disposed above said control region;

    a source contact region formed of said first conductivity type, said control region and said inner region being at least partly disposed between said source contact region and said drain contact region;

    a first connection region formed of said first conductivity type, said first connection region having at least one inner part running within said semiconductor region substantially perpendicularly to said first surface, said first connection region directly connected to said source contact region in a low-impedance manner and being doped more highly than said inner region forming a current path between said source contact region and said drain contact region having lower losses in a forward-biasing situation than for a current flow via said inner region; and

    a second connection region formed of said second conductivity type and having at least one inner part running within said semiconductor region substantially perpendicularly to said first surface, said second connection region compensating for an influence of said first connection region in a reverse-biasing situation.

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