Semiconductor device of SOI structure

• US 6,693,326 B2
• Filed: 04/02/2001
• Issued: 02/17/2004
• Est. Priority Date: 04/04/2000
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Adan, Alberto O.
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/822,251
• Publication Number:
  US 20010028089A1
• Time in Patent Office: 1,051 Days
• Field of Search: 257/347, 257/348, 257/349, 257/359, 257/376, 257/387
• US Class Current: 257/347
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.

Claims

1. A semiconductor device including SOI structure, the semiconductor device comprising:

a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to form an SOI substrate,

source/drain regions of second conductivity type which are formed in the surface semiconductor layer,

a channel region of first conductivity type between the source/drain regions,

a gate electrode formed over the channel region and a gate insulating film,

wherein the surface semiconductor layer comprises only a single potential well of the first conductivity type formed therein at and/or near only one end of the channel region in a gate width direction thereof and wherein a first part of the potential well includes an impurity concentration higher than that of the channel region so as to cause majority carriers to migrate toward the potential well, and

wherein a second part of the potential well not having an impurity concentration higher than that of the channel region has a length (Lpn) that is longer than a length (Wpn) of the first part of the potential well that has an impurity concentration higher than that of the channel region.

2. A semiconductor device as defined in claim 1, wherein the potential well is formed in self-alignment with the gate electrode.

3. A semiconductor device as defined in claim 1, wherein the potential well is formed near ends of the source/drain regions and between the source/drain regions.

4. A semiconductor device as defined in claim 1, wherein the potential well has a length Lpn which does not cause a short channel effect incurring a potential fall in the gate length direction.

5. A semiconductor device as defined in claim 4, wherein the potential well is longer than a gate length of the gate electrode in a gate length direction.

6. A semiconductor device as defined in claim 5, wherein the potential well has 1.5 times or more the length of the gate length L of the gate electrode.

7. A semiconductor device as defined in claim 1, wherein the potential well is set in an electrically floating state.

8. A semiconductor device as defined in claim 1, wherein the potential well further contains an inert element and/or germanium as an impurity.

9. A semiconductor device as defined in claim 1, wherein the inert element and/or germanium is contained in a concentration range of 10¹⁶ to 10¹⁸ cm⁻

3, respectively.

10. A semiconductor device as defined in claim 1, wherein the source/drain regions are so deep as to reach the buried oxide film.

11. A semiconductor device as defined in claim 1, wherein the potential well is so deep as to reach the buried oxide film.

12. A semiconductor device as defined in claim 1, wherein the potential well has an impurity concentration in a range of 3×

10¹⁶ to 10¹⁸ cm^{31 3}.

14. The semiconductor device of claim 1, wherein the first part of the potential well has an impurity concentration from 2-10 times higher than the channel region.

13. A semiconductor device comprising:

a SOI (Silicon-On-Insulator) substrate including a surface semiconductor layer in a floating state,

a channel region located between source and drain regions formed in the surface semiconductor layer, wherein the channel region is of a first conductivity type and the source/drain regions are of a second conductivity type different than the first conductivity type;

a gate electrode formed over the channel region; and

wherein the surface semiconductor layer further comprises only one potential well of the first conductivity type formed therein at or near only one end of the channel region, and wherein only a first part of the potential well includes an impurity concentration higher than that of the channel region so as to cause holes or majority carriers to migrate toward the potential well, and wherein the first part of the potential well has a length (Wpn) less than a length (Lpn) of the potential well.

15. The semiconductor device of claim 13, wherein the first part of the potential well has an impurity concentration from 2-10 times higher than the channel region.