Contact structure for group III-V semiconductor devices and method of producing the same

• US 6,693,352 B1
• Filed: 06/05/2000
• Issued: 02/17/2004
• Est. Priority Date: 06/05/2000
• Status: Expired due to Fees

• Current Assignee: Emitronix Incorporated
• Original Assignee: Emitronix Incorporated
• Inventors: Li, Youming, Huang, Wingo
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US09/587,014
• Time in Patent Office: 1,352 Days
• Field of Search: 257/743, 257/744, 257/745, 257/99
• US Class Current: 257/743
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 33/28 containing only elements of Group II and Group VI of the Periodic Table
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: H01S 5/0421 characterised by the semiconducting contacting layers electrodes H01S5/0425

Abstract

A contact structure for group III-V and group II-VI compound semiconductor devices, generally used as a light emitting diode (LED), a laser diode (LD), or a photodiode (PD), comprising p-type and/or n-type conduction is disclosed. The contact structure comprises a stack of multiple layers of metals and transparent conducting oxide. The first layer of the contact structure is in direct contact to the semiconductor and comprises at least one of indium, tin, nickel, chromium and zinc, or an alloy or combination of layers thereof. The second layer of the structure is in direct contact to the first layer and comprises at least one of Indium Tin Oxide, Indium oxide, and Tin oxide, or a combination thereof. The optional third layer of the structure contacts the second layer and comprises at least one of Au, Al, Pt, Pd, Mo, Cr, Rh, Ti. The third layer may be a contact pad contacting a smaller portion of the second layer. A preferred thermal anneal of one or more layers of the contact structure further improves semiconductor device performance.

Claims

1. A contact structure for a compound semiconductor device having p-type or n-type conduction, comprising:

a first plurality layer structure having at least a first contact layer of metal selected from the group consisting of Indium, Tin, Zinc and alloys thereof contacting a group III-V compound semiconductor and a second contact layer of transparent conducting oxide selected from the group consisting of Indium-Tin-Oxide, Indium-Oxide, Tin-Oxide and Zinc-Oxide being formed on said first contact layer; and

a second layer structure including a metal pad formed on said first plurality layer structure.

2. A contact structure according to claim 1, wherein said first plurality layer structure has undergone a thermal anneal at an elevated temperature.

3. A contact structure according to claim 2, wherein said thermal anneal was performed in a temperature range between about 200°

C. and 700°

C.

4. A contact structure according to claim 2, wherein said thermal anneal was performed under in an atmosphere including at least one gaseous species selected from the group of gaseous species consisting of air, nitrogen, oxygen, argon, and helium.

5. A contact structure according to claim 1, wherein said metal pad of said second layer structure comprises at least one element selected from the group of elements consisting of Aluminum (Al), Gold (Au), Chromium (Cr), Molybdenum (Mo), Nickel (Ni), Palladium (Pd), Platinum (Pt), Rhodium (Rh), Tantalum (Ta), and Titanium (Ti).

6. A contact structure according to claim 1, wherein said first contact layer of said first plurality layer structure comprises Indium, and said second contact layer of transparent conducting oxide of said first plurality layer structure comprises Indium-Tin-oxide (ITO).

7. A contact structure according to claim 1, wherein said first contact layer of said first plurality structure comprises Indium, and said second contact layer of transparent conducting oxide of said first plurality structure comprises Indium-oxide (In₂O₃).

8. A contact structure according to claim 1, wherein said first contact layer of said first plurality structure comprises Indium, and said second contact layer of transparent conducting oxide of said first plurality structure comprises Tin-oxide (SnO₂).

9. A contact structure according to claim 1, wherein said first contact layer of said first plurality layer structure comprises tin, and said second contact layer of transparent conducting oxide of said first plurality layer structure comprises Indium-Tin-oxide (ITO).

16. A contact structure according to claim 1, wherein said first contact layer of said first plurality structure has a thickness in a range between about 5 Angstroms and 1000 Angstroms.

17. A contact structure according to claim 16, wherein said second contact layer of transparent conducting oxide of said first plurality structure has a thickness in a range between about 100 Angstroms and 50,000 Angstroms.

18. A contact structure according to claim 17, wherein said metal pad of said second layer structure has a thickness in a range between about 100 Angstroms and 50,000 Angstroms.

19. A contact structure according to claim 1, wherein said second contact layer of transparent conducting oxide of said first plurality structure has a thickness in a range between about 100 Angstroms and 50,000 Angstroms.

20. A contact structure according to claim 1, wherein said metal pad of said second layer structure has a thickness in a range between about 100 Angstroms and 50,000 Angstroms.

21. A contact structure according to claim 5, wherein said metal pad of said second layer structure has a thickness in a range between about 100 Angstroms and 50,000 Angstroms.

22. A contact structure according to claim 5, wherein said metal pad of said second layer structure is configured for connection with electronic circuitry by a method selected from the group of methods consisting of wire-bonding and anisotropic conductive film bonding.

28. A group III-V compound semiconductor device having contact structure as in claim 1 further comprising:

a substrate; and

a group III-V semiconductor plurality layer structure formed on said substrate,

wherein said contact structure is formed on said group III-V semiconductor plurality layer structure.

29. A semiconductor device as in claim 28, wherein said group III-V semiconductor layers comprise A1_xGa_yIn₁₋

x−

yN, where 0<

=x<

=1, 0<

=y<

=1, and 0<

=x+y<

=1 inclusive.

30. A semiconductor device of claim 29, wherein said group III-V compound semiconductor device is a device selected from the group of devices consisting of a light-emitting diode (LED), a laser diode (LD), and a photodiode (PD).

31. A semiconductor device as in claim 28, wherein said group III-V semiconductor plurality layer structure comprises A1_xGa_y,In₁₋

x−

y,As_zP,<sub>1−

z</sub>, wherein 0<

=x<

=1, 0<

=y<

=1, 0<

=x+y<

=1, 0<

=z<

=1 inclusive.

32. A semiconductor device as in claim 31, wherein said group III-V compound semiconductor device is a device selected from the group of devices consisting of a light emitting diode (LED), a laser diode (LD) and a photodiode (PD).

33. A semiconductor device as in claim 28, wherein said substrate comprises an insulator.

34. A semiconductor device as in claim 33, wherein said insulator comprises sapphire.

35. A semiconductor device as in claims 34, wherein said non-insulating material comprises doped silicon-carbide.

36. A group II-VI compound semiconductor device having contact structure as in claim 1, and further comprising:

a substrate; and

a group II-VI semiconductor plurality layer structure formed on said substrate,

wherein said contact structure is formed on said group II-VI semiconductor plurality layer structure.

38. The contact structure of claim 1, wherein the first contact layer comprises a plurality layer structure of at least two elements.

39. The contact structure of claim 38, wherein the first contact layer has undergone a thermal anneal between depositions of the at least two elements.

40. The contact structure of claim 39, wherein said at least two elements include nickel over indium.

41. The contact structure of claim 39, wherein said at least two elements include indium over nickel.

42. The contact structure of claim 38, wherein the first contac layer has undergone a thermal anneal after deposition of the at least two elements.

43. The contact structure of claim 42, wherein said at least two elements include nickel over indium.

44. The contact structure of claim 42, wherein

said at least two elements include indium over nickel.

45. The contact structure of claim 1, wherein the first contact layer comprises an alloy of the at least two elements.

46. The contact structure of claim 45, wherein the at least two elements include nickel and indium.

47. The contact structure of claim 45, wherein said plurality layer structure has undergone a thermal anneal at an elevated temperature.

48. The contact structure of claim 47, wherein the at least two elements include nickel and indium.

54. A semiconductor device as in claim 28, wherein said substrate comprises a non-insulating material.

10. A contact structure for a compound semiconductor device having p-type or n-type conduction, comprising:

a first plurality layer structure having at least a first contact layer of metal contacting a group III-V compound semiconductor and a second contact layer of transparent conducting oxide being formed on said first contact layer; and

a second layer structure including a metal pad formed on said first plurality layer structure,

wherein said first contact layer of said first plurality structure comprises tin, and said second contact layer of transparent conducting oxide of said first plurality structure comprises Indium-oxide (In₂O₃).

15. A contact structure according to claims 6-14, wherein said first plurality layer structure has undergone a thermal anneal at an elevated temperature, and wherein said thermal anneal is performed in a temperature range from about 200°

C. to 700°

C.

23. A contact structure as in any of claims 3 or 6-14, wherein said thermal anneal was performed in an atmosphere of nitrogen.

24. A contact structure according to any of claims 3 or 6-14, wherein said thermal anneal was performed in an atmosphere of air.

25. A contact structure according to any of claims 3 or 6-14, wherein said thermal anneal was performed in an atmosphere of oxygen.

26. A contact structure according to claims 3 or 6-14, wherein said thermal anneal was performed in an evacuated atmosphere.

11. A contact structure for a compound semiconductor device having p-type or n-type conduction, comprising:

a first plurality layer structure having at least a first contact layer of metal contacting a group III-V compound semiconductor and a second contact layer of transparent conducting oxide being formed on said first contact layer; and

a second layer structure including a metal pad formed on said first plurality layer structure,

wherein said first contact layer of said first plurality structure comprises tin, and said second contact layer of transparent conducting oxide of said first plurality structure comprises Tin-oxide (SnO₂).

27. A contact structure according to any of claims 8, 11 or 14, wherein said second contact layer of transparent conducting oxide further comprises indium-tin-oxide.

12. A contact structure for a compound semiconductor device having p-type or n-type conduction, comprising:

a first plurality layer structure having at least a first contact layer of metal contacting a group III-V compound semiconductor and a second contact layer of transparent conducting oxide being formed on said first contact layer; and

a second layer structure including a metal pad formed on said first plurality layer structure,

wherein said first contact layer of said first plurality layer structure comprises zinc, and said second contact layer of transparent conducting oxide of said first plurality layer structure comprises Indium-Tin-oxide (ITO).

13. A contact structure for a compound semiconductor device having p-type or n-type conduction, comprising:

a first plurality layer structure having at least a first contact layer of metal contacting a group III-V compound semiconductor and a second contact layer of transparent conducting oxide being formed on said first contact layer; and

a second layer structure including a metal pad formed on said first plurality layer structure,

wherein said first contact layer of said first plurality structure comprises zinc, and said second contact layer of transparent conducting oxide of said first plurality structure comprises Indium-oxide (In₂O₃).

14. A contact structure for a compound semiconductor device having p-type or n-type conduction, comprising:

a first plurality layer structure having at least a first contact layer of metal contacting a group III-V compound semiconductor and a second contact layer of transparent conducting oxide being formed on said first contact layer; and

a second layer structure including a metal pad formed on said first plurality layer structure,

wherein said first contact layer of said first plurality structure comprises zinc, and said second contact layer of transparent conducting oxide of said first plurality structure comprises Tin-oxide (SnO₂).

37. A contact electrode for a compound semiconductor device having an active region and at least one of a p+-conduction layer and a n+-conduction layer, comprising:

a thin annealed metal layer with a small portion removed over one of said at least one of said p+-conduction layer and said n+-conduction layer of said device, said thin metal layer being partially inter-diffused in said conduction layer;

a transparent conducting oxide layer selected from the group consisting of Indium-Oxide, Tin-Oxide and Zinc-Oxide over said thin annealed metal layer and over said small portion of said conduction layer and having said thin annealed metal layer partially inter-diffused therein, said transparent conducting oxide layer over said thin annealed metal layer for spreading current over a wider active region than a metal pad over said transparent conducting oxide layer, said transparent conducting oxide layer over said small portion of said conduction layer and creating Schottky barrier with said conduction layer for current blocking, thereby reducing the current flow into said small portion of said conduction layer and increasing the light output of the device; and

said metal pad contact over a fractional portion of said transparent conducting oxide layer which at least partially overlaps an area including where said small portion of said thin metal contact layer was removed, wherein the thin annealed metal layer is selected from the group consisting of Indium, Tin, Zinc and alloys thereof.

49. A contact electrode for a compound semiconductor device having an active region and at least one of a p+-conduction layer and a n+ conduction layer, comprising:

a thin annealed metal layer comprising Indium over one of said at least one of said p+-conduction layer and said n+-conduction layer of said device, said thin metal layer being partially inter-diffused in said one of said at least one of said p+ conduction layer and said n+-conduction layer;

a transparent conducting oxide layer over said thin annealed metal layer and having said thin annealed metal layer partially inter-diffused therein, said transparent conducting oxide layer over said thin annealed metal layer for spreading current over a wider active region than a metal pad contact over said transparent conducting oxide layer;

said metal pad contact over a fractional portion of said transparent conducting oxide layer.

50. The contact electrode of claim 49, wherein the transparent conducting oxide layer is selected from the group consisting of Indium-Tin-Oxide, Indium-Oxide, Tin-Oxide and Zinc-Oxide.

51. The contact electrode of claim 49, wherein the transparent conducting oxide layer comprises Indium-Tin-Oxide.

52. The contact electrode of claim 51, wherein the thin annealed metal layer further comprises at least one from the group consisting of nickel, chromium, tin, zinc and alloys of nickel, chromium, tin, zinc and indium.

53. The contact electrode of claim 49, wherein the thin annealed metal layer further comprises at least one from the group consisting of nickel, chromium, tin, zinc and alloys of nickel, chromium, tin, zinc and indium.