Method of driving a display device
First Claim
Patent Images
1. A method of driving a display device, said method comprising the steps of:
- inputting a first current into a pixel;
converting the first current into a voltage;
holding the voltage;
converting the voltage into a second current;
inputting the second current into a light emitting element of the pixel;
wherein the light emitting element emits a light with a constant luminance;
dividing one frame period into a plurality of sub frame periods, wherein whether the pixel emits the light or not is determined in each of the plurality of sub frame periods.
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Abstract
A driving method that does not allow a change in temperature of the surroundings to change the luminance of a light emitting element of a pixel is provided for a display device with less uneven display, higher gradation, and reduced power consumption. A time ratio gradation driving method is applied to a pixel that is structured to have a current mirror circuit and use a current drive method. The bit number of digital video signals to be sampled by a source signal line driving circuit is reduced with the use of a switching signal, thereby saving the power consumption when high gradation display is not necessary.
117 Citations
61 Claims
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1. A method of driving a display device, said method comprising the steps of:
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inputting a first current into a pixel;
converting the first current into a voltage;
holding the voltage;
converting the voltage into a second current;
inputting the second current into a light emitting element of the pixel;
wherein the light emitting element emits a light with a constant luminance;
dividing one frame period into a plurality of sub frame periods, wherein whether the pixel emits the light or not is determined in each of the plurality of sub frame periods. - View Dependent Claims (2, 3)
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4. A method of driving a display device, said display device comprising:
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a pixel including a first thin film transistor, a second thin film transistor and a light emitting element;
said method comprising the steps of;
inputting a first current into the pixel;
wherein the first current is a first drain current of the first thin film transistor operated in a saturation range;
holding a first gate voltage of the first thin film transistor;
wherein the first gate voltage of the first thin film transistor is a second gate voltage of the second thin film transistor;
inputting a second drain current of the second thin film transistor into the light emitting element;
wherein the light emitting element emits a light with a constant luminance;
dividing one frame period into a plurality of sub frame periods, wherein whether the pixel emits the light or not is determined in each of the plurality of sub frame periods. - View Dependent Claims (5, 6)
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7. A method of driving a display device, said display device comprising:
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a plurality of pixels;
a driver circuit inputted with n bits digital signals, wherein n is a natural number;
said method comprising the steps of;
inputting a constant signal current into each of the plurality of pixels;
wherein each of the plurality of pixels emits a light with a constant luminance by the constant signal current;
dividing one frame period into a plurality of sub frame periods;
selecting an output of a constant current into each of the plurality of pixels in accordance with each of a first bit digital signal to an n-th bit digital signal among the n bits digital signals by the driver circuit in each of the plurality of sub frame periods,wherein whether the pixel emits the light or not is determined in each of the plurality of sub frame periods. - View Dependent Claims (8, 9, 10, 11)
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12. A method of driving a display device, said display device comprising:
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a source signal line driving circuit;
a gate signal line driving circuit;
a selection line driving circuit; and
a pixel portion, said pixel portion comprising;
a plurality of pixels;
a plurality of source signal lines;
a plurality of gate signal lines; and
a plurality of power supply lines, each of the plurality of pixels including;
a switching thin film transistor;
a current mirror circuit comprising a first thin film transistor and a second thin film transistor; and
a light emitting element, wherein a gate electrode of the first thin film transistor is connected to a gate electrode of the second thin film transistor, said method comprising the steps of;
inputting a signal current from the source signal line driving circuit into the plurality of source signal lines;
selecting one of the plurality of gate signal lines by the gate signal line driving circuit;
inputting a current into the light emitting element from one of the plurality of power supply lines through a source region and a drain region of the second thin film transistor in a pixel in which a source region and drain region of the switching thin film transistor is turned conductive;
wherein the light emitting element emits a light, wherein whether or not the signal current is outputted to the plurality of source signal lines is selected to determine whether the light emitting element emits the light or not, wherein a luminance is determined by the total length of time the light emitting element emits the light in one frame period. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 59)
wherein each of the plurality of sub frame periods includes a display period in which whether or not the light emitting element in each of the plurality of pixels emits a light is determined. -
14. A method according to claim 13, further comprising the step of:
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inputting n bits digital video signals from an external, wherein n is a natural number, wherein the plurality of sub frame period include r sub frame periods, wherein r is a natural number equal to or larger than n, wherein n periods are combined with display periods of the r sub frame periods, wherein a ratio of lengths of the n periods is set to 20;
2−
1;
2−
2;
. . . ;
2(n−
1);
2−
(n−
1).
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15. A method according to claim 13, further comprising the step of:
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inputting n-bits digital video signals from an external, wherein n is a natural number, wherein the plurality of sub frame periods include n sub frame periods; and
wherein a ratio of lengths of respective display periods of the n sub frame periods is set to 20;
2−
1;
2−
2;
. . . ;
2−
(n−
2);
2−
(n−
1).
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16. A method according to claim 13, wherein m bits digital video signals are not sampled by the source signal line driving circuit,
wherein m is a natural number smaller than n. -
17. A method according to claim 16, wherein the m bits digital video signals correspond to lower m bits digital video signals of the n bits digital video signals.
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18. A method according to claim 17, wherein sub frame periods corresponding to the lower m bits digital video signals include no-sampling-pulse periods in which a shift register in the source signal line driving circuit stops outputting sampling pulses.
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19. A method according to claim 18, wherein the display device includes a start pulse controlling circuit for changing a start pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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20. A method according to claim 19, wherein the start pulse controlling circuit comprises at least a NAND and at least an inverter,
wherein the start pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the start pulse controlling circuit through the inverter. -
21. A method according to claim 18, wherein the display device includes a clock pulse controlling circuit for changing a clock pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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22. A method according to claim 21, wherein the clock pulse controlling circuit comprises at least a NAND 10 and at least an inverter, wherein the clock pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the clock pulse controlling circuit through the inverter.
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23. A method according to claim 18, wherein the display device includes a sampling pulse controlling circuit for changing a sampling pulse to be outputted from the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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24. A method according to claim 23, wherein the sampling pulse controlling circuit comprises at least a NAND and at least an inverter, wherein the sampling pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the sampling pulse controlling circuit through the inverter.
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25. A method according to claim 17, wherein sub frame periods corresponding to the lower m bits digital video signals include, reset periods, and no-sampling-pulse periods in which a shift register in the source signal line driving circuit stops outputting sampling pulses.
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26. A method according to claim 25, wherein the display device includes a reset circuit for changing the digital video signals into an output of a constant electric potential, and
wherein a ‘ - 0’
signal is inputted from the reset circuit to the source signal line driving circuit during the reset period to be sampled, andwherein the ‘
0’
signal is outputted to the plurality of source signal lines.
- 0’
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27. A method according to claim 26, wherein the reset circuit comprises at least a NAND and at least an inverter,
wherein the digital video signals and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the reset circuit through the inverter. -
28. A method according to claim 25, wherein the display device includes a start pulse controlling circuit for changing a start pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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29. A method according to claim 28, wherein the start pulse controlling circuit comprises at least a NAND and at least an inverter, wherein the start pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the start pulse controlling circuit through the inverter.
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30. A method according to claim 25, wherein the display device includes a clock pulse controlling circuit for changing a clock pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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31. A method according to claim 30, wherein the clock pulse controlling circuit comprises at least a NAND and at least an inverter, wherein the clock pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the clock pulse controlling circuit through the inverter.
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32. A method according to claim 25, wherein the display device includes a sampling pulse controlling circuit for changing a sampling pulse to be outputted from the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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33. A method according to claim 32, wherein the sampling pulse controlling circuit comprises at least a NAND and at least an inverter, wherein the sampling pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the sampling pulse controlling circuit through the inverter.
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34. A method according to claim 12, wherein the light emitting element comprises an organic material in a light emitting layer.
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35. A method according to claim 12, wherein the light emitting element comprises an inorganic material in a light emitting layer.
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36. A method according to claim 12, wherein the display device is in combination with an electronic apparatus, wherein the electronic apparatus is one selected from the group consisting of a portable information terminal, a personal computer, an image reproducing device, a television, a head-mounted display and a video camera.
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59. A method according to claim 31, wherein the light emitting element comprises an organic material in a light emitting layer.
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37. A method of driving a display device, said display device comprising:
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a source signal line driving circuit;
a gate signal line driving circuit;
a selection line driving circuit; and
a pixel portion, said pixel portion comprising;
a plurality of pixels;
a plurality of source signal lines;
a plurality of gate signal lines;
a plurality of power supply lines; and
a plurality of selection lines, each of the plurality of pixels including;
a first switching thin film transistor;
a second switching thin film transistor;
a current mirror circuit comprising a first thin film transistor and a second thin film transistor; and
a light emitting element, wherein one of a source region and drain region of the first switching thin film transistor is connected to one of the plurality of source signal lines, wherein the other of the source and drain regions of the first switching thin film transistor is connected to one of a source region and a drain region of the second switching thin film transistor and to one of a source region and a drain region of the first thin film transistor, wherein a gate electrode of the first switching thin film transistor is connected to one of the plurality of gate signal lines, wherein the other of the source drain regions of the second switching thin film transistor is connected to a gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor, wherein the other of the source drain regions of the first thin film transistor is connected to one of the plurality of power supply lines, wherein a gate electrode of the second switching thin film transistor is connected to one of the plurality of selection lines, wherein one of a source region and a drain region of the second thin film transistor is connected to one of the plurality of power supply lines, wherein the other of the source region and drain regions of the second thin film transistor is connected to the light emitting element, said method comprising the steps of;
inputting a signal current into the plurality of source signal lines from the source signal line driving circuit;
selecting one of the plurality of gate signal lines by the gate signal line driving circuit;
selecting one of the plurality of selection lines by the selection line driving circuit;
wherein the signal current flows between the source and drain regions of the first thin film transistor in a pixel in which the source and drain regions of the first switching thin film transistor is turned conductive and the source and drain regions of the second switching thin film transistor is turned conductive;
inputting a current into the light emitting element from one of the plurality of power supply lines through a source region and a drain region of the second thin film transistor, wherein whether or not the signal current is outputted to the plurality of source signal lines is selected to determine whether the light emitting element emits the light or not, wherein a luminance is determined by the total length of time the light emitting element emits the light in one frame period. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 60, 61)
inputting n-bits digital video signals from an external, wherein n is a natural number, wherein the plurality of sub frame periods include n sub frame periods; and
wherein a ratio of lengths of respective display periods of the n sub frame periods is set to 20;
2−
1;
2−
2;
. . . ;
2−
(n−
2);
2−
(n−
1).
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41. A method according to claim 38, wherein m bits digital video signals are not sampled by the source signal line driving circuit, wherein m is a natural number smaller than n.
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42. A method according to claim 41, wherein the m bits digital video signals correspond to lower m bits digital video signals of the n bits digital video signals.
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43. A method according to claim 42, wherein sub frame periods corresponding to the lower m bits digital video signals include no-sampling-pulse periods in which a shift register in the source signal line driving circuit stops outputting sampling pulses.
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44. A method according to claim 43, wherein the display device includes a start pulse controlling circuit for changing a start pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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45. A method according to claim 44, wherein the start pulse controlling circuit comprises at least a NAND and at least an inverter,
wherein the start pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the start pulse controlling circuit through the inverter. -
46. A method according to claim 43, wherein the-display device includes a clock pulse controlling circuit for changing a clock pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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47. A method according to claim 46, wherein the clock pulse controlling circuit comprises at least a NAND and at least an inverter,
wherein the clock pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the clock pulse controlling circuit through the inverter. -
48. A method according to claim 43, wherein the display device includes a sampling pulse controlling circuit for changing a sampling pulse to be outputted from the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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49. A method according to claim 48, wherein the sampling pulse controlling circuit comprises at least a NAND and at least an inverter,
wherein the start pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the clock pulse controlling circuit through the inverter. -
50. A method according to claim 43, wherein sub frame periods corresponding to the lower m bits digital video signals include, reset periods, and no-sampling-pulse periods in which a shift register in the source signal line driving circuit stops outputting sampling pulses.
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51. A method according to claim 50, wherein the display device includes a reset circuit for changing the digital video signals into an output of a constant electric potential, and
wherein a ‘ - 0’
signal is inputted from the reset circuit to the source signal line driving circuit during the reset period to be sampled, andwherein the ‘
0’
signal is outputted to the plurality of source signal lines.
- 0’
-
52. A method according to claim 51, wherein the reset circuit comprises at least a NAND and at least an inverter,
wherein the digital video signals and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the reset circuit through the inverter. -
53. A method according to claim 50, wherein the display device includes a start pulse controlling circuit for changing a start pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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54. A method according to claim 53, wherein the start pulse controlling circuit comprises at least a NAND and at least an inverter,
wherein the start pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the start pulse controlling circuit through the inverter. -
55. A method according to claim 50, wherein the display device includes a clock pulse controlling circuit for changing a clock pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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56. A method according to claim 55, wherein the clock pulse controlling circuit comprises at least a NAND and at least an inverter,
wherein the clock pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the sampling pulse controlling circuit through the inverter. -
57. A method according to claim 50, wherein the display device includes a sampling pulse controlling circuit for changing a sampling pulse to be outputted from the shift register into an output of a constant electric potential during the no-sampling-pulse period.
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58. A method according to claim 57, wherein the sampling pulse control circuit comprises at least a NAND and at least an inverter,
wherein the sampling pulse and switching signals are inputted to the NAND, and wherein signals outputted from the NAND are outputted from the sampling pulse controlling circuit through the inverter. -
60. A method according to claim 37, wherein the light emitting element comprises an inorganic material in a light emitting layer.
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61. A method according to claim 37, wherein the display device is in combination with an electronic apparatus,
wherein the electronic apparatus is one selected from the group consisting of a portable information terminal, a personal computer, an image reproducing device, a television, a head-mounted display and a video camera.
Specification