Floor planning for programmable gate array having embedded fixed logic circuitry

• US 6,693,452 B1
• Filed: 02/25/2002
• Issued: 02/17/2004
• Est. Priority Date: 02/25/2002
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ansari, Ahmad R., Douglass, Stephen M.
• Primary Examiner(s): LE, DON P
• Application Number:
  US10/082,883
• Time in Patent Office: 722 Days
• Field of Search: 326/37-41
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17732 Macroblocks
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Interconnecting logic provides connectivity of an embedded fixed logic circuit, or circuits, with programmable logic fabric of a programmable gate array such that the fixed logic circuit functions as an extension of the programmable logic fabric. The interconnecting logic includes interconnecting tiles and may further include interconnecting logic. The interconnecting tiles provide selective connectivity between inputs and/or outputs of the fixed logic circuit and the interconnects of the programmable logic fabric. The interconnecting logic, when included, provides logic circuitry that conditions data transfers between the fixed logic circuit and the programmable logic fabric. The invention is directed towards the various needs and requirements of the layout and floor planning of a device having both fixed logic circuitry and programmable logic circuitry. The various designs are geared towards many goals including allowing fail-safe operation, facilitating the ease of interface between fixed logic circuitry and programmable logic fabric, among other issues.

Claims

1. An integrated circuit comprising:

a plurality of configurable logic blocks arranged into a fabric, the fabric having an opening therein that is surrounded by configurable logic blocks;

a fixed logic circuit residing in the opening, wherein the fixed logic circuit includes a plurality of input/output lines;

interconnecting logic residing in the opening that interfaces the plurality of input/output lines to the fabric; and

wherein the interconnecting logic distributes the plurality of input/output lines along a plurality of configurable logic blocks bordering the opening.

2. The integrated circuit of claim 1, wherein:

the input/output lines include address lines and data lines; and

each of the plurality of configurable logic blocks services at least one address line and at least one data line of the plurality of input/output lines.

3. The integrated circuit of claim 1, wherein:

the input/output lines include address lines, data lines, and control lines; and

each of the plurality of configurable logic blocks services at least one address line, at least one data line, and at least one control line of the plurality of input/output lines.

4. The integrated circuit of claim 1, wherein:

the input/output lines include address lines, data in lines, data out lines, and control lines; and

each of the plurality of configurable logic blocks services at least one address line, at least one data in line, at least one data out line, and at least one control line of the plurality of input/output lines.

5. The integrated circuit of claim 1, wherein each of the plurality of the configurable logic blocks surrounding the opening services a plurality of address lines and a plurality of data lines of the plurality of input/output lines.

6. The integrated circuit of claim 1, wherein the plurality of the configurable logic blocks define a first side of the opening and service a plurality of address lines and a plurality of data lines of the plurality of input/output lines.

7. An integrated circuit comprising:

a plurality of configurable logic blocks arranged into a fabric, the fabric having an opening therein that is surrounded by configurable logic blocks;

a fixed logic circuit residing in the opening, wherein the fixed logic circuit includes a plurality of input/output lines;

interconnecting logic residing in the opening that interfaces the plurality of input/output lines to the fabric; and

wherein the interconnecting logic distributes the plurality of input/output lines along a plurality of configurable logic blocks bordering a first side of the opening.

8. The integrated circuit of claim 7, wherein:

the input/output lines include address lines, data lines, and control lines; and

each of the plurality of configurable logic blocks services at least one address line, at least one data line, and at least one control line of the plurality of input/output lines.

9. The integrated circuit of claim 7, wherein:

the input/output lines include address lines, data in lines, data out lines, and control lines; and

each of the plurality of configurable logic blocks services at least one address line, at least one data in line, at least one data out line, and at least one control line of the plurality of input/output lines.

10. An integrated circuit comprising:

a plurality of configurable logic blocks arranged into a fabric, the fabric having a first opening and a second opening formed therein, each of which is surrounded by configurable logic blocks;

a first fixed logic circuit residing in the first opening, wherein the first fixed logic circuit includes a first plurality of input/output lines;

a second fixed logic circuit residing in the second opening, wherein the second fixed logic circuit includes a second plurality of input/output lines;

first interconnecting logic residing in the first opening that interfaces the first plurality of input/output lines to the fabric;

second interconnecting logic residing in the second opening that interfaces the second plurality of input/output lines to the fabric; and

wherein the first interconnecting logic and the second interconnecting logic symmetrically interface the first plurality of input/output lines and the second plurality of input/output lines to the fabric.

11. The integrated circuit of claim 10, wherein:

the first opening resides in a first side of the fabric;

the second opening resides in a second side of the fabric;

the first side of the fabric and the second side of the fabric are divided by a center line of the fabric; and

the first plurality of input/output lines and the second plurality of input/output lines are symmetrically interfaced to the fabric about the center line of the fabric.

12. The integrated circuit of claim 10, wherein:

the fabric includes block RAM arranged into a plurality of block RAM strips;

the first opening bisects a first block RAM strip into an upper portion and a lower portion;

the second opening bisects a second block RAM strip into an upper portion and a lower portion;

the upper portions of the first and second block RAM strips are employed for instruction storage by the first and second fixed logic circuits, respectively; and

the lower portions of the first and second block RAM strips are employed for data storage by the first and second fixed logic circuits, respectively.

13. The integrated circuit of claim 10, wherein:

the fabric includes block RAM arranged into a plurality of block RAM strips;

the first opening bisects a first block RAM strip into an upper portion and a lower portion;

the second opening bisects a second block RAM strip into an upper portion and a lower portion;

the upper portions of the first and second block RAM strips are employed for data storage by the first and second fixed logic circuits, respectively; and

the lower portions of the first and second block RAM strips are employed for instruction storage by the first and second fixed logic circuits, respectively.

14. The integrated circuit of claim 10, wherein:

the fabric includes block RAM arranged into a plurality of block RAM strips;

the first opening bisects a first set of block RAM strips into an upper portion and a lower portion;

the second opening bisects a second set of block RAM strips into an upper portion and a lower portion;

the upper portions of the first and second sets of block RAM strips are employed for instruction storage by the first and second fixed logic circuits, respectively; and

the lower portions of the first and second sets of block RAM strips are employed for data storage by the first and second fixed logic circuits, respectively.

15. The integrated circuit of claim 10, wherein:

the fabric includes block RAM arranged into a plurality of block RAM strips;

the first opening bisects a first set of block RAM strips into an upper portion and a lower portion;

the second opening bisects a second set of block RAM strips into an upper portion and a lower portion;

the upper portions of the first and second sets of block RAM strips are employed for data storage by the first and second fixed logic circuits, respectively; and

the lower portions of the first and second sets of block RAM strips are employed for instruction storage by the first and second fixed logic circuits, respectively.

16. The integrated circuit of claim 10, wherein the first fixed logic circuit and the second fixed logic circuit comprise substantially identical circuits.

17. The integrated circuit of claim 10, wherein:

the first opening resides in a first side of the fabric;

the second opening resides in a second side of the fabric;

the first side of the fabric and the second side of the fabric are divided by a center line of the fabric; and

the first plurality of input/output lines and the second plurality of input/output lines extend from the first fixed logic circuit and the second fixed logic circuit symmetrically about the center line of the fabric.

18. An integrated circuit comprising:

a plurality of configurable logic blocks arranged into a fabric, the fabric having a first opening, a second opening, a third opening, and a fourth opening formed therein, each of which is surrounded by configurable logic blocks;

a first fixed logic circuit residing in the first opening, wherein the first fixed logic circuit includes a first plurality of input/output lines;

a second fixed logic circuit residing in the second opening, wherein the second fixed logic circuit includes a second plurality of input/output lines;

first interconnecting logic residing in the first opening that interfaces the first plurality of input/output lines to the fabric;

second interconnecting logic residing in the second opening that interfaces the second plurality of input/output lines to the fabric; and

wherein the first interconnecting logic and the second interconnecting logic symmetrically interface the first plurality of input/output lines and the second plurality of input/output lines to the fabric.

19. The integrated circuit of claim 18, further comprising:

a third fixed logic circuit residing in the third opening, wherein the third fixed logic circuit includes a third plurality of input/output lines;

a fourth fixed logic circuit residing in the fourth opening, wherein the fourth fixed logic circuit includes a fourth plurality of input/output lines;

third interconnecting logic residing in the third opening that interfaces the third plurality of input/output lines to the fabric;

fourth interconnecting logic residing in the fourth opening that interfaces the fourth plurality of input/output lines to the fabric; and

wherein the third interconnecting logic and the fourth interconnecting logic symmetrically interface the third plurality of input/output lines and the fourth plurality of input/output lines to the fabric.

20. The integrated circuit of claim 19, wherein:

the fabric includes four quadrants;

the first fixed logic circuit and the second fixed logic circuit reside in lower quadrants of the four quadrants; and

the third fixed logic circuit and the fourth fixed logic circuit reside in upper quadrants of the four quadrants.

21. The integrated circuit of claim 19, wherein:

the fabric includes four quadrants;

the first fixed logic circuit and the second fixed logic circuit reside in right quadrants of the four quadrants; and

the third fixed logic circuit and the fourth fixed logic circuit reside in left quadrants of the four quadrants.

22. The integrated circuit of claim 19, wherein:

the fabric includes block RAM arranged into a plurality of block RAM strips;

the first opening bisects a first block RAM strip into an upper portion and a central portion;

the second opening bisects a second block RAM strip into an upper portion and a central portion;

the third opening bisects the first block RAM strip into the central portion and a lower portion;

the fourth opening bisects the second block RAM strip into the central portion and a lower portion;

the upper portions of the block RAM strips are employed for instruction storage by the first and second fixed logic circuits; and

the lower portions of the first and second block RAM strips are employed for instruction storage by the third and fourth fixed logic circuits, respectively.

23. The integrated circuit of claim 22, wherein:

the central portion of the first block RAM strip is employed for data storage by the first and second fixed logic circuits; and

the central portion of the second block RAM strip is employed for data storage by the third and fourth fixed logic circuits.

24. A method for designing an integrated circuit, the method comprising:

arranging a plurality of configurable logic blocks into a fabric;

removing a group of the configurable logic blocks from the fabric to form an opening in the fabric that is surrounded by configurable logic blocks;

placing a fixed logic circuit in the opening, wherein the fixed logic circuit includes a plurality of input/output lines;

placing interconnecting logic in the opening that interfaces the plurality of input/output lines to the fabric; and

wherein the interconnecting logic distributes the plurality of input/output lines along a plurality of configurable logic blocks bordering of the opening.

25. The method of claim 24, wherein:

the input/output lines include address lines and data lines; and

the interfacing circuit causes each of the plurality of the configurable logic blocks to service at least one address line and at least one data line of the plurality of input/output lines.

26. The method of claim 24, wherein:

the input/output lines include address lines, data lines, and control lines; and

wherein each of the plurality of the configurable logic blocks services at least one address line, at least one data line, and at least one control line of the plurality of input/output lines.

27. The method of claim 24, wherein:

the input/output lines include address lines, data in lines, data out lines, and control lines; and

each of the plurality of the configurable logic blocks services at least one address line, at least one data in line, at least one data out line, and at least one control line of the plurality of input/output lines.

28. The method of claim 24, wherein each of the plurality of the configurable logic blocks surrounding the opening services a plurality of address lines and a plurality of data lines of the plurality of input/output lines.

29. The method of claim 24, wherein the plurality of the configurable logic blocks define a first side of the opening and service a plurality of address lines and a plurality of data lines of the plurality of input/output lines.

30. A method for designing an integrated circuit, the method comprising:

arranging a plurality of configurable logic blocks into a fabric;

removing a group of the configurable logic blocks from the fabric to form an opening in the fabric that is surrounded by configurable logic blocks;

placing a fixed logic circuit in the opening, wherein the fixed logic circuit includes a plurality of input/output lines;

placing interconnecting logic residing in the opening that interfaces the plurality of input/output lines to the fabric; and

wherein the interconnecting logic distributes the plurality of input/output lines along a plurality of configurable logic blocks forming a first side of the opening.

31. The method of claim 30, wherein:

the input/output lines include address lines, data lines, and control lines; and

each of the plurality of configurable logic blocks services at least one address line, at least one data line, and at least one control line of the plurality of input/output lines.

32. The method of claim 30, wherein:

the input/output lines include address lines, data in lines, data out lines, and control lines; and

each of the plurality of configurable logic blocks services at least one address line, at least one data in line, at least one data out line, and at least one control line of the plurality of input/output lines.

33. A method for designing an integrated circuit, the method comprising:

arranging a plurality of configurable logic blocks into a fabric;

removing a first group of the configurable logic blocks to form a first opening in the fabric that is surrounded by configurable logic blocks;

removing a second group of the configurable logic blocks to form a second opening in the fabric that is surrounded by configurable logic blocks;

placing a first fixed logic circuit in the first opening, wherein the first fixed logic circuit includes a first plurality of input/output lines;

placing a second fixed logic circuit in the second opening, wherein the second fixed logic circuit includes a second plurality of input/output lines;

placing first interconnecting logic in the first opening that interfaces the first plurality of input/output lines to the fabric;

placing second interconnecting logic in the second opening that interfaces the second plurality of input/output lines to the fabric; and

wherein the first interconnecting logic and the second interconnecting logic symmetrically interface the first plurality of input/output lines and the second plurality of input/output lines to the fabric.

34. The method of claim 33, wherein:

the first opening resides in a first side of the fabric;

the second opening resides in a second side of the fabric;

the first side of the fabric and the second side of the fabric are divided by a center line of the fabric; and

the first plurality of input/output lines and the second plurality of input/output lines are symmetrically interfaced to the fabric about the center line of the fabric.

35. The method of claim 33, further comprising forming a plurality of block RAM strips in the fabric, wherein:

the first opening bisects a first block RAM strip into an upper portion and a lower portion;

the second opening bisects a second block RAM strip into an upper portion and a lower portion;

the upper portions of the first and second block RAM strips are employed for instruction storage by the first and second fixed logic circuits, respectively; and

the lower portions of the first and second block RAM strips are employed for data storage by the first and second fixed logic circuits, respectively.

36. The method of claim 35, wherein the first fixed logic circuit and the second fixed logic circuit comprise substantially identical circuits.

37. The method of claim 33, wherein:

the first opening resides in a first side of the fabric;

the second opening resides in a second side of the fabric;

the first side of the fabric and the second side of the fabric are divided by a center line of the fabric; and

the first plurality of input/output lines and the second plurality of input/output lines extend from the first fixed logic circuit and the second fixed logic circuit symmetrically about the center line of the fabric.

38. A method for designing integrated circuit, the method comprising:

arranging a plurality of configurable logic blocks arranged into a fabric;

removing four groups of configurable logic blocks from the fabric to form a first opening, a second opening, a third opening, and a fourth opening in the fabric, each opening being surrounded by configurable logic blocks;

placing a first fixed logic circuit in the first opening, wherein the first fixed logic circuit includes a first plurality of input/output lines;

placing a second fixed logic circuit in the second opening, wherein the second fixed logic circuit includes a second plurality of input/output lines;

placing first interconnecting logic in the first opening that interfaces the first plurality of input/output lines to the fabric;

placing second interconnecting logic in the second opening that interfaces the second plurality of input/output lines to the fabric; and

wherein the first interconnecting logic and the second interconnecting logic symmetrically interface the first plurality of input/output lines and the second plurality of input/output lines to the fabric.

39. The method of claim 38, further comprising:

placing a third fixed logic circuit in the third opening, wherein the third fixed logic circuit includes a third plurality of input/output lines;

placing a fourth fixed logic circuit in the fourth opening, wherein the fourth fixed logic circuit includes a fourth plurality of input/output lines;

placing third interconnecting logic in the third opening that interfaces the third plurality of input/output lines to the fabric;

placing fourth interconnecting logic in the fourth opening that interfaces the fourth plurality of input/output lines to the fabric; and

wherein the third interconnecting logic and the fourth interconnecting logic symmetrically interface the third plurality of input/output lines and the fourth plurality of input/output lines to the fabric.

40. The method of claim 39, wherein:

the fabric includes four quadrants;

the first fixed logic circuit and the second fixed logic circuit reside in lower quadrants of the four quadrants; and

the third fixed logic circuit and the fourth fixed logic circuit reside in upper quadrants of the four quadrants.

41. The method of claim 39, wherein:

the fabric includes four quadrants;

the first fixed logic circuit and the second fixed logic circuit reside in right quadrants of the four quadrants; and

the third fixed logic circuit and the fourth fixed logic circuit reside in left quadrants of the four quadrants.

42. The method of claim 39, wherein:

the fabric includes block RAM arranged into a plurality of block RAM strips;

the first opening bisects a first block RAM strip into an upper portion and a central portion;

the second opening bisects a second block RAM strip into an upper portion and a central portion;

the third opening bisects the first block RAM strip into the central portion and a lower portion;

the fourth opening bisects the second block RAM strip into the central portion and a lower portion;

the upper portions of the block RAM strips are employed for instruction storage by the first and second fixed logic circuits; and

the lower portions of the first and second block RAM strips are employed for instruction storage by the third and fourth fixed logic circuits, respectively.

43. The method of claim 42, wherein:

the central portion of the first block RAM strip is employed for data storage by the first and second fixed logic circuits; and

the central portion of the second block RAM strip is employed for data storage by the third and fourth fixed logic circuits.