Voltage booster with increased voltage boost using two pumping capacitors

• US 6,693,480 B1
• Filed: 03/27/2003
• Issued: 02/17/2004
• Est. Priority Date: 03/27/2003
• Status: Active Grant

• Current Assignee: Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Wong, Anthony Yap
• Primary Examiner(s): NGUYEN, LONG T
• Application Number:
  US10/249,282
• Time in Patent Office: 327 Days
• Field of Search: 827/108, 827/112, 827/389, 827/390, 827/306, 827/536, 363/59, 363/60
• US Class Current: 327/390
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H03K 17/063 in field-effect transistor switches

Abstract

A voltage booster drives the gate of a bus-switch n-channel transistor to a theoretical maximum of triple the power-supply voltage Vcc. The gate node is first driven to Vcc. Then the back-side of a first capacitor is driven from ground to Vcc, coupling a first voltage boost to the gate node. After a Schmidt-trigger detects the back-side of the first capacitor near Vcc, the back-side of a second capacitor is driven from ground to Vcc. The front-side of the second capacitor is connected to the back-side of the first capacitor. A second voltage boost is coupled across the first and second capacitors to increase the voltage boost of the gate node to near triple Vcc rather than just double Vcc.

Claims

1. A double-boost voltage booster comprising:

a buffer for buffering an input signal to generate a buffered input signal;

a charge pump for generating a pumped voltage above a power-supply voltage;

a boosted node driven from ground to a boosted voltage above the power-supply voltage;

a pull-down n-channel transistor, coupled to drive the boosted node to ground in response to the buffered input signal;

a pull-up p-channel transistor, having a gate controlled by the buffered input signal, for coupling the boosted node to a keeper node;

a keeper p-channel transistor, coupled to supply a keeper current to the keeper node from the charge pump, the keeper p-channel transistor having a keeper gate;

a control node, initially driven low in response to the buffered input signal;

a first p-channel transistor, having a drain coupled to the boosted node and a source coupled to a power source providing the power-supply voltage, for conducting current from the power source to the boosted node in response to the control node applied to a gate of the first p-channel transistor;

a second p-channel transistor, having a drain coupled to the control node and a source coupled to the pumped voltage from the charge pump, for conducting current from the pumped voltage to the control node, the second p-channel transistor having a gate controlled by a delayed node;

a first delay line, having a first inverter with an input connected to the boosted node, for delaying a rising transition of the boosted node to drive the delayed node to control the second p-channel transistor and for driving a first back-side node;

a first capacitor, coupled between the first back-side node and the boosted node, for coupling a first voltage swing output by the first delay line to the boosted node;

a second delay line, having a second inverter with an input connected to the first back-side node, for delaying a rising transition of the first back-side node to drive a second back-side node; and

a second capacitor, coupled between the first back-side node and the second back-side node, for coupling a second voltage swing output by the second delay line to the first back-side node,

whereby the first voltage swing is coupled to the boosted node through the first capacitor and the second voltage swing is coupled to the boosted node through the first and second capacitors.

2. The double-boost voltage booster of claim 1 wherein the boosted node is driven toward a theoretical maximum of three times the power-supply voltage.

3. The double-boost voltage booster of claim 1 wherein the first inverter in the first delay line comprises a first Schmidt-trigger inverter and wherein the second inverter in the second delay line comprises a second Schmidt-trigger inverter.

4. The double-boost voltage booster of claim 3 wherein the first Schmidt-trigger inverter has a high input threshold, an output of the first Schmidt-trigger inverter being driven low once the boosted node nears the power-supply voltage, and wherein the second Schmidt-trigger inverter has a high input threshold, an output of the second Schmidt-trigger inverter being driven low once the first back-side node nears the power-supply voltage.

5. The double-boost voltage booster of claim 4 wherein a leakage current is drawn from the charge pump by the double-boost voltage booster, the leakage current being a few microamps.

6. The double-boost voltage booster of claim 5 wherein the first capacitor is a p-channel transistor with a gate connected to the boosted node and a source and a drain connected together to the first back-side node, and wherein the second capacitor is a p-channel transistor with a gate connected to the first back-side node and a source and a drain connected together to a second back-side node.

7. The double-boost voltage booster of claim 6 further comprising:

an n-channel pullup transistor, having a gate controlled by the first delay line, for driving the control node to a threshold voltage below the power-supply voltage, the n-channel pullup transistor being activated by the first delay line before the second p-channel transistor is activated,

whereby the control node is first pulled high by the n-channel pullup transistor and then pulled to the pumped voltage by the second p-channel transistor.

8. The double-boost voltage booster of claim 7 further comprising:

a first control pull-down transistor, having a gate controlled by the buffered input signal, for pulling the control node down to ground;

a second control pull-down transistor, coupled in series with the first control pull-down transistor, having a gate controlled by the first inverter in the first delay line, for isolating the control node from ground;

wherein the first control pull-down transistor and the second control pull-down transistor are n-channel transistors.

9. The double-boost voltage booster of claim 8 wherein the boosted node is coupled to a gate of a bus-switch transistor, the bus-switch transistor having a lower on-resistance when the boosted node is at the boosted voltage than at the power-supply voltage.

10. The double-boost voltage booster of claim 9 further comprising:

a logic gate having an input connected to the buffered input signal and another input coupled to the second back-side node, for driving the keeper gate of the keeper p-channel transistor;

wherein the logic gate is connected to the pumped voltage from the charge pump and not connected to the power-supply voltage,

whereby the logic gate outputs the pumped voltage rather than the power-supply voltage.

11. The double-boost voltage booster of claim 10 wherein the logic gate is a NAND gate.

12. The double-boost voltage booster of claim 9 wherein the first delay line has a final inverter for driving the first back-side node;

wherein the final inverter is connected to the pumped voltage from the charge pump.

13. A voltage-boosted bus switch comprising:

an input signal for controlling when the voltage-boosted bus switch is to isolate and when the voltage-boosted bus switch is to connect a first node and a second node;

a bus-switch transistor, coupled between the first node and the second node, the bus-switch transistor conducting current between the first node and the second node in response to a boosted node coupled to a gate of the bus-switch transistor;

a first pullup transistor, coupled to drive the boosted node toward a power-supply voltage, the first pullup transistor having a gate connected to a control node;

control pulldown means for discharging the control node in response to the input signal;

first voltage sensor means, coupled to the boosted node, for sensing a voltage of the boosted node when the boosted node has been charged to near the power-supply voltage by the first pullup transistor;

control isolation means, coupled between the control pulldown means and the control node, for isolating the control node in response to the first voltage sensor means detecting that the boosted node is near the power-supply voltage;

control pullup means, responsive to the first voltage sensor means, for charging the control node and disabling the first pullup transistor when the first voltage sensor means detects that the boosted node is near the power-supply voltage;

first capacitor means, coupled between the boosted node and a first back node, for capacitively coupling a first voltage swing of the first back node into the boosted node when the first voltage sensor means detects that the boosted node is near the power-supply voltage;

second voltage sensor means, coupled to the first back node, for sensing a voltage of the first back node when the first back node has been charged to near the power-supply voltage; and

second capacitor means, coupled between the first back node and a second back node, for capacitively coupling a second voltage swing of the second back node into the first back node when the second voltage sensor means detects that the first back node is near the power-supply voltage;

wherein the second voltage swing is further coupled to the boosted node by the first capacitor means,

whereby the boosted node is boosted twice above the power-supply voltage.

14. The voltage-boosted bus switch of claim 13 wherein the first voltage sensor means comprises a first Schmidt-trigger inverter having a higher input threshold for rising input transitions than for falling input transitions and wherein the second voltage sensor means comprises a second Schmidt-trigger inverter having a higher input threshold for rising input transitions than for falling input transitions.

15. A double voltage booster circuit comprising:

an input signal;

a boosted node;

a control node, the control node initially driven low by a transition of the input signal;

a first pull-up, coupled to the boosted node, for pulling the boosted node to a power-supply voltage in response to the control node;

a first voltage sensor, coupled to the boosted node, for sensing a voltage of the boosted node when the boosted node is pulled up to near the power-supply voltage;

a first delay line, coupled to the first voltage sensor, for generating a delayed signal in response to the boosted node being pulled up toward the power-supply voltage, the first delay line also for generating another delay signal for driving the control node high after a delay;

a first capacitor, coupled to the boosted node and responsive to the delayed signal on a first back node, for capacitively coupling a first voltage swing of the first back node into the boosted node in response to the delayed signal, the first voltage swing boosting a voltage of the boosted node to a first boosted voltage above the power-supply voltage;

a second voltage sensor, coupled to the first back node, for sensing a voltage of the first back node when the first back node is driven to near the power-supply voltage;

a second delay line, coupled to the second voltage sensor, for generating a second delayed signal on a second back node in response to the first back node being pulled up toward the power-supply voltage; and

a second capacitor, coupled to the first and second back nodes and responsive to the second delayed signal, for capacitively coupling a second voltage swing of the second back node into the first back node in response to the second delayed signal, the second voltage swing boosting a voltage of the first back node to a voltage above the power-supply voltage, the first capacitor then boosting the boosted node to a second boosted voltage above the power-supply voltage, the second boosted voltage being above the first boosted voltage,

whereby the boosted node is boosted twice by capacitive coupling through the first and second capacitors.

16. The double voltage booster circuit of claim 15 further comprising:

a charge pump for generating a pumped voltage above the power-supply voltage.

17. The double voltage booster circuit of claim 16 further comprising:

a keeper pull-up device, coupled to the boosted node and coupled to the charge pump, for supplying a compensating current to the boosted node, the compensating current sufficient to offset leakage currents from the boosted node but not sufficient to pull the boosted node up to the pumped voltage.

18. The double voltage booster circuit of claim 17 wherein the keeper pull-up device is further coupled to the sec delayed signal from the second delay line, the keeper pull-up device being enabled by the second delayed signal.

19. The double voltage booster circuit of claim 18 further comprising:

a second pullup device, controlled by the first delay line, for driving the control node high after a delay when the first voltage sensor senses that the boosted node is near the power-supply voltage;

a control-node pulldown device, responsive to the transition on the input signal, for initially driving the control node low;

an isolation transistor, coupled between the control-node pulldown device and the control node, for isolating the control-node pulldown device from the control node once the first voltage sensor senses that the boosted node is near the power-supply voltage.

20. The double voltage booster circuit of claim 19 wherein the boosted node is coupled to a gate of a bus-switch transistor, the bus-switch transistor driving a greater current when the boosted node is at the second boosted voltage than at the power-supply voltage.