SPDT switch and communication unit using the same

• US 6,693,498 B1
• Filed: 01/16/2001
• Issued: 02/17/2004
• Est. Priority Date: 02/22/2000
• Status: Expired due to Fees

• Current Assignee: Murata Manufacturing Co Limited
• Original Assignee: Murata Manufacturing Co Limited
• Inventors: Sasabata, Akihiro, Nakao, Motoyasu, Okamoto, Shigekazu
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Jones, Stephen E.
• Application Number:
  US09/760,862
• Time in Patent Office: 1,127 Days
• Field of Search: 333/103, 333/101, 333/104, 333/262, 455/78
• US Class Current: 333/103
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

An SPDT switch used for a communication unit includes first and second terminals, a common terminal, and first and second FETs with Schottky connection gates. The drain of the first FET is connected to the first terminal, and the source of the second FET is connected to the second terminal. The source of the first FET and the drain of the second FET are directly connected to each other, and are then connected to the common terminal. The pinch-off voltage V_p1 of the first FET is set to satisfy 0 >V_p1>α−γ, and the pinch-off voltage V_p2 of the second FET is set to satisfy 0 >V_p2>γ−β, where α<γ<β. A fixed potential γ is applied to the gate of the second FET, and one of potentials α and β is applied to the gate of the first FET, so that one of the first and second terminals can be electrically connected to the common terminal. Additional resonance and/or switching elements may be included as well.

Claims

1. An SPDT switch comprising:

a first terminal;

a second terminal;

a common terminal; and

first and second FETs each having two respective main terminals and respective Schottky connection gates;

wherein one main terminal of said first FET and one main terminal of said second FET are connected to said first terminal and said second terminal, respectively;

the other main t terminal of said first FET and the other main terminal of said second FET are connected to said common terminal;

a fixed potential γ

is applied to the gate of said second FET, and one of potentials α and

β

are applied to the gate of said first FET without changing the fixed potential applied to the gate of said second FET, where α

<

γ

<

β

, to allow one of said first and second terminals to be electrically connected to said common terminal; and

the pinch-off voltage 0>

V_p1>

α

−

γ

, and the pinch-off voltage V_p2 of said second FET is set to satisfy 0>

V_p2>

γ

−

β

.

2. An SPDT switch according to claim 1, further comprising:

a first inductor connected in parallel to said first FET; and

a second inductor connected in parallel to said second FET.

3. An SPDT switch according to claim 1, further comprising:

a first inductor connected in series to said first FET;

a first capacitor connected in parallel to the series connection of said first FET and said first inductor;

a second inductor connected in series to said second FET; and

a second capacitor connected in parallel to the series connection of said second FET and said second inductor.

4. An SPDT switch according to claim 1, further comprising:

a third FET having two main terminals and a Schottky connection gate, having a pinch-off voltage V_p3 set to satisfy 0>

V_p3>

γ

−

β

; and

a fourth FET having two main terminals and a Schottky connection gate, having a pinch-off voltage V_p4 set to satisfy 0>

V_p4>

α

−

γ

,

wherein said third FET has one main terminal connected to said one main terminal of said first FET, the other main terminal connected to ground via a first ground capacitor, and a gate connected to the gate of said second FET; and

said fourth FET has one main terminal connected to said one main terminal of said second FET, the other main terminal connected to ground via a second ground capacitor, and a gate connected to the gate of said first FET.

5. A communication unit including an SPDT switch according to any of claims 1 to 4;

a transmitter circuit connected to one of said first and second terminals;

a receiver circuit connected to the other of said first and second terminals; and

a control circuit connected to said gate of said first FET for applying thereto said one of said potentials α and

β

.