Modulation of a digital input signal using a digital signal modulator and signal splitting

• US 6,693,571 B2
• Filed: 12/20/2002
• Issued: 02/17/2004
• Est. Priority Date: 05/10/2000
• Status: Active Grant

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Andersen, Jack B., Chorn, Michael G., Melanson, John L.
• Primary Examiner(s): JEAN PIERRE, PEGUY
• Application Number:
  US10/325,145
• Publication Number:
  US 20030095013A1
• Time in Patent Office: 424 Days
• Field of Search: 341/143, 341/144, 330/10, 375/238
• US Class Current: 341/143
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/2173 of the bridge type
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

A digital signal modulator modulates a digital input signal to drive a load, such as an opposed current amplifier or other opposed current converter. The combinations of frequency relationships and digital signal modulator elements provide significant digital signal processing capabilities and flexible output signal timing. In one embodiment, a digital signal modulator modulates a digital input signal. Even and odd samples of the input signal propagate along two respective channels (signal paths), which include further digital processing capabilities, such as pulse width modulation, to generate output signals appropriate for the topology of a load. Additionally, a bias signal may be modulated with the digital input signal. By utilizing digital signal processing to modulate the input signal, various processing technologies are applied to the input signal. For example, noise shaping may be implemented using a delta-sigma modulator as an input stage to the two channels.

Claims

1. An apparatus comprising:

a first digital signal modulator to generate a first modulated output signal derived from a digital input signal; and

first duty cycle circuitry, coupled to the first digital signal modulator, to receive first and second input signals, which are respective subsets of samples of the first modulated output signal, wherein the first duty cycle circuitry responds to the first and second input signals and respectively generates a first output signal and a second output signal;

wherein during operation of the first digital signal modulator and the first duty cycle circuitry, a duty cycle of the first output signal has a direct relationship to change in the digital input signal, a duty cycle of the second output signal has an inverse relationship to change in the digital input signal, and the first and second output signals are suitable for driving an opposed current converter stage.

2. The apparatus of claim 1 further comprising:

biasing circuitry to positively bias approximately one-half of samples of the digital input signal and to negatively bias a remainder of the digital input signal samples when a bias signal is nonzero.

3. The apparatus of claim 2 wherein the digital input signal is sampled a frequency, f_s, the biasing circuitry further comprises:

a multiplier having (i) inputs to receive the bias signal V_b and a waveform having a frequency of f_s/2 and (ii) circuitry to multiply V_b and the waveform to alternately generate V_b and minus V_b; and

wherein the first modulated output signal is derived from the digital input signal and bias signal V_b.

4. The apparatus of claim 3 wherein the digital input signal and bias signal V_b are separately received by the first digital signal modulator.

5. The apparatus of claim 2 wherein the first and second output signals of the duty cycle circuitry have approximately equal duty cycles when the first and second input signals are equal and the bias signal is zero.

6. The apparatus of claim 1 further comprising:

a delay element, coupled to an output of the circuitry, to delay the first output signal relative to the second output signal.

7. The apparatus of claim 5 further comprising:

a second digital signal modulator to generate a second modulated output signal derived from the digital input signal;

second duty cycle circuitry, coupled to the second digital signal modulator, to receive third and fourth input signals, which are respective subsets of samples of the second modulated output signal, wherein the second duty cycle circuitry responds to the third and fourth input signals and respectively generates a third output signal and a fourth output signal;

wherein during operation of the second digital modulator and the second duty cycle circuitry, a duty cycle of the third output signal has a direct relationship to change in the digital input signal, a duty cycle of the fourth output signal has an inverse relationship to change in the digital input signal, and the third and fourth output signals are suitable for driving an opposed current converter stage;

a first amplifier having a first switch, coupled between a first voltage source and a load, with a control terminal to receive the first output signal and having a second switch, coupled between a second voltage source and the load, with a control terminal to receive the second output signal; and

a second amplifier having a first switch, coupled between the first voltage source and the load, with a control terminal to receive the third output signal and having a second switch, coupled between the second voltage source and the load, with a control terminal to receive the fourth output signal.

8. The apparatus of claim 1 wherein:

the first output signal is operable to control a first switch;

the second output signal is operable to control a second switch; and

a duty cycle of the first switch has an inverse relationship to a duty cycle of the second switch if the digital input signal has a non-zero magnitude.

9. The apparatus of claim 8 wherein the change in the digital input signal comprises a change in magnitude of the digital input signal.

10. The apparatus of claim 1 further comprising:

an analog output stage coupled to the first duty cycle circuitry and having (i) respective inputs to receive the first and second output signals, and (ii) circuitry to convert the first and second output signals into a single analog output signal.

11. The apparatus of claim 10 wherein the analog output stage comprises an opposed current converter circuit, wherein the opposed current converter circuit comprises:

a positive current control switch to receive the first output signal;

a negative current control switch to receive the second output signal; and

an output terminal coupled between the positive current control switch and the negative current control switch for supplying current to a load.

12. The apparatus of claim 1 wherein:

the first digital signal modulator comprises a delta-sigma modulator to receive and process the first digital input signal;

the first duty cycle circuitry further comprises (i) a first duty cycle demodulator to process alternate samples of the first modulated output signal and (ii) a second duty cycle demodulator to process samples of the first modulated output signal not processed by the first duty cycle demodulator.

13. The apparatus as in claim 12 wherein the first and second duty cycle demodulators respectively include first and second pulse width modulators.

14. The apparatus of claim 12 further comprising:

a clock to provide interleaved clock signals to the first and second duty cycle demodulators.

15. The apparatus of claim 1 wherein the first digital signal modulator includes noise-shaping capabilities to reduce audio frequency noise.

16. The apparatus of claim 1 wherein the digital input signal is an audio signal.

17. The apparatus of claim 1 further comprising:

M sets of the first digital signal modulator, each having an input to receive the first digital input signal and an output to provide a modulated output signal; and

M sets of the first duty cycle modulator coupled to an associated set of the M first digital signal modulators, each having an input to receive the output signal of the associated M first circuitry and outputs to provide multiple output signals;

wherein M is a positive integer greater than 1.

18. A digital to analog converter system comprising:

a first modulator having an input to receive a digital input signals derived from a common input signal and a bias signal and an output to provide a first modulated signal, wherein the first modulated signal is comprised of a first and second group of signals;

a first duty cycle modulator coupled to the first modulator to receive the first group of signals and generate output signals corresponding to the first group of signals; and

a second duty cycle modulator coupled to the first modulator to receive the second group of signals and generate output signals corresponding to the second group signals.

19. The digital to analog converter system of claim 18 further comprising:

an analog output stage coupled to the duty cycle modulators and having a first input to receive the output signals from the first duty cycle modulator, a second input to receive the output signals from the second duty cycle modulator, and circuitry to convert the received output signals into a drive signal that provides current to a load.

20. The digital to analog converter system of claim 19 wherein the analog output stage is an opposed current power converter circuit.

21. The digital to analog converter system of claim 18 wherein the first group of the digital input signals is derived from the common input signal and a positive version of the bias signal and the second group of the digital input signals is derived from the common input signal and a positive version of the bias signal.

22. The digital to analog converter system of claim 21 wherein the first group of the digital input signals consists of even numbered digital input signals and the second group of the digital input signals consists of odd numbered digital input signals.

23. The digital to analog converter system of claim 18 wherein:

the first modulator includes a delta-sigma modulator;

the first duty cycle modulator includes a pulse width modulator; and

the second duty cycle modulator includes another pulse width modulator.

24. The digital to analog converter system of claim 18 further comprising:

M additional duty cycle modulators coupled to the first modulator, wherein the Y^th duty cycle modulator receives the Y^th group of the M signals and generates output signals corresponding to the Y^th group of the M signals,

wherein M is an integer greater than 2 and Y is an integer ranging from 3 through M.

25. An apparatus comprising:

means for generating a first digital input signal from a common input signal and a first bias signal and for generating a second digital input signal from the common input signal and a second bias signal;

means for (i) modulating the first digital input signal, coupled to the means for generating the first and second digital input signals, to generate N modulated first output signals, wherein N is a positive integer and (ii) modulating the second digital input signal to generate N modulated second output signals;

means for providing (i) the first output signals to first circuitry and (ii) the second output signals to second circuitry; and

means for converting the N and M modulated output signals into a drive signal.

26. The apparatus of claim 25 wherein the means for converting comprises an opposed current converter.

27. The apparatus of claim 25 wherein the first and second bias signals are arithmetic complements.

28. A method of providing multiple output drive signals derived from a common input signal, the method comprising:

receiving a common digital input signal and a first digital bias signal;

converting the common digital input signal and the first digital bias signal into a first output signal using a first modulator;

receiving the common digital input signal and a second digital bias signal;

converting the common digital input signal and the second digital bias signal into a second output signal using the first modulator; and

providing the first and second output signals to circuitry operable to derive a drive signal from the first and second output signals.

29. The method of claim 28 wherein:

converting the common digital input signal and the first digital bias signal comprises modulating the first digital input signal with a delta-sigma modulator to generate a first delta-sigma output signal;

converting the common digital input signal and the second digital bias signal comprises modulating the second digital input signal with the delta-sigma modulator to generate a second delta-sigma output signal; and

providing the first and second output signals to circuitry operable to derive a drive signal comprises;

providing the first output signal to a first duty cycle modulator and providing an output signal of the first duty cycle modulator to an opposed current converter; and

providing the second output signal to a second duty cycle modulator and providing an output signal of the second duty cycle modulator to the opposed current converter.

30. The method of claim 28 further comprising:

utilizing the first and second output signals to cause an opposed current converter to provide the drive signal as an output signal.

31. The method of claim 28 wherein the common digital input signal is sampled at a frequency f_s, the method further comprising:

multiplying a digital bias signal times a signal oscillating between logical 1 and −

1 at a frequency of f_s/2;

generating the first digital bias signal from the digital biasing signal times logical 1; and

generating the second digital bias signal from the digital biasing signal times logical −

1.

32. The method of claim 28 further comprising:

shaping noise frequencies of the first and second output signals.

33. The method of claim 32 wherein shaping noise frequencies comprises locating noise frequencies outside of audio frequencies.

34. The method of claim 28 wherein the first and second output signals are approximately in-phase when the common digital input signal plus the first digital equals the common digital input signal plus the second digital bias signal.

35. The method of claim 28 wherein the first and second digital bias signals are arithmetic complements.

36. The method of claim 28 further comprising:

inverting the second output signal.

37. The method of claim 28 wherein the first output signal is derived from even samples of the common input signal and the second output signal is derived from odd samples of the common input signal.

38. The method of claim 28 further comprising:

converting the common digital input signal and the first digital bias signal into N additional output signals using N modulators, wherein N is a positive integer;

converting the common digital input signal and a second digital bias signal into M additional output signals using M modulators, wherein M is a positive integer; and

converting the first and second output signals and the N and M additional output signals into drive signals.

39. The method of claim 28 wherein the circuitry includes a half bridge opposed current converter.

40. A method of providing multiple output signals derived from a common digital input signal, the method comprising:

generating first output signals derived from the digital input signal using a first digital signal modulator;

providing a first group of the first output signals to circuitry for processing the first output signals into signals suitable for driving circuitry in an opposed current converter stage; and

providing a second group of the first output signals to circuitry for processing the first output signals into signals suitable for driving circuitry in the opposed current converter stage;

wherein the first output signals have a direct relationship to change in the digital input signal and the second output signals have an inverse relationship to change in the digital input signal.

41. The method of claim 40 wherein:

generating the first output signals comprises modulating the digital input signal using a delta-sigma modulator;

providing the first group of the first output signals comprises providing even numbers of the first output signals to first duty cycle modulation circuitry; and

providing the first group of the first output signals comprises providing odd numbers of the first output signals to second duty cycle modulation circuitry.