Multi-channel bit-serial analog-to-digital converter with reduced channel circuitry
First Claim
1. An analog-to-digital converter circuit, comprising:
- a first signal generator for generating a first signal having a plurality of levels;
a comparator, wherein a first part of said comparator is formed within each of a plurality of input channels that generate analog input signals and a remaining part of said comparator is formed external to said input channels and is shared by said input channels, wherein said comparator is controlled by a selection signal as to which analog input signal is to be compared with said first signal;
a binary signal generator for generating a series of binary signals; and
a one-bit latch having a first input coupled to receive an output of said comparator, said latch having a data input coupled to receive said binary signals, an output of said comparator controlling when said latch provides an output signal corresponding to a binary signal applied to said data input, wherein said latch is formed external to said input channels and is shared by said input channels;
wherein said latch provides at least a portion of an N-bit digital code representing said analog input applied to said comparator.
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Abstract
A multi-channel bit-serial analog-to-digital converter with reduced channel circuitry is described herein in which a one-bit comparator circuit is split between a first part located within an input channel and a second part located outside the input channel. The external part of the comparator and the one-bit latch are shared by a plurality of input channels. In the preferred embodiment, a two-dimensional sensor array of pixel elements is fabricated in a single integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are formed in the periphery of the sensor array and are shared by a group of pixel elements, such as a column of pixel elements. In one embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can also be used as a buffer for analog readout. This creates an analog read port for minimum amount of circuitry increase.
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Citations
21 Claims
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1. An analog-to-digital converter circuit, comprising:
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a first signal generator for generating a first signal having a plurality of levels;
a comparator, wherein a first part of said comparator is formed within each of a plurality of input channels that generate analog input signals and a remaining part of said comparator is formed external to said input channels and is shared by said input channels, wherein said comparator is controlled by a selection signal as to which analog input signal is to be compared with said first signal;
a binary signal generator for generating a series of binary signals; and
a one-bit latch having a first input coupled to receive an output of said comparator, said latch having a data input coupled to receive said binary signals, an output of said comparator controlling when said latch provides an output signal corresponding to a binary signal applied to said data input, wherein said latch is formed external to said input channels and is shared by said input channels;
wherein said latch provides at least a portion of an N-bit digital code representing said analog input applied to said comparator. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for converting electrical signals representing an optical image into binary signals, said method comprising:
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receiving a first signal having a plurality of levels;
comparing said first signal to an analog input signal to be converted into digital value and outputting a comparison result, wherein said analog input signal is sequentially selected from N analog input signals by a selection signal, wherein each of said analog input signals is generated by each of a plurality of input channels respectively;
receiving a series of binary signals; and
applying said comparison result to a first input of a latch, and applying said series of binary signals to a data input of said latch, wherein a logic level of said comparison result controlling when said latch provides an output signal corresponding to a binary signal applied to said data input, and wherein said latch provides at least a portion of an N-bit digital code representing said analog input signal. - View Dependent Claims (19, 20, 21)
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Specification