Integration type A/D conversion method, integration type A/D converter, and battery charger utilizing such converter

• US 6,693,577 B2
• Filed: 07/16/2002
• Issued: 02/17/2004
• Est. Priority Date: 07/19/2001
• Status: Expired due to Fees

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Yamamoto, Kenji
• Primary Examiner(s): JEANGLAUDE, JEAN BRUNER
• Application Number:
  US10/198,201
• Publication Number:
  US 20030016154A1
• Time in Patent Office: 581 Days
• Field of Search: 341/155, 324/436, 324/428, 327/77, 320/132
• US Class Current: 341/155
• CPC Class Codes: H03M 1/52 Input signal integrated with linear return to datum

Abstract

In the invention, an integrator integrates a current indicative of an input signal to generate at its output end a voltage (referred to as integral output voltage) by means of a condenser. At a point in time when the integral output voltage has reached a predetermined level, or at a point in time determined by timing of a predetermined period, the integral output voltage is reduced in absolute value by flowing into or out of the condenser a constant current supplied by a constant current source. The direction of the constant current depends on the polarity of the output of the integrator. A counter counting up or down clocks stops counting while the constant current is flowing. This permits use of a low-frequency A/D converter to convert the input signal at a reduced power and extend the dynamic range of the A/D converter.

Claims

1. An integration type A/D converter, comprising:

an integration circuit for integrating an input signal to generate an integral output voltage;

an integral output voltage reduction circuit for bringing said integral output voltage back to the initial level thereof by a predetermined magnitude per unit time upon receipt of an integral output voltage reduction signal;

a comparison circuit having at least one comparator for comparing said integral output voltage with a predetermined value to generate a comparative output;

a counter for counting clocks upon receipt of a signal instructing counting clocks (said signal hereinafter referred to as count instruction signal); and

a control circuit for generating, upon receipt of said comparative output, said integral output voltage reduction signal and said count instruction signal, and wherein said comparison circuit has

a first comparator for generating a first comparative output when said integral output voltage exceeds in absolute value a negative predetermined level;

a second comparator for generating a second comparative output when said integral output voltage is substantially zero; and

a third comparator for generating a third comparative output when said integral output voltage exceeds a positive predetermined level,

said counter is an up-down counter that counts up said clocks upon receipt of an up-count instruction signal and counts down said clocks upon receipt of a down-count signal; and

said control circuit generates said integral output voltage reduction signal and up-count instruction signal during a period which begins with the generation of said first comparative output and ends with the generation of said second comparative output, and generates said integral output voltage reduction signal and said down-count instruction signal during a period which begins with the generation of said third comparative output and ends with the generation of said second comparative output.

2. A battery charger having an integration type A/D converter, said A/D converter comprising:

an integration circuit for integrating an input signal to generate an integral output voltage;

an integral output voltage reduction circuit for bringing said integral output voltage back to the initial level thereof by a predetermined magnitude per unit time upon receipt of an integral output voltage reduction signal;

a comparison circuit having at least one comparator for comparing said integral output voltage with a predetermined value to generate a comparative output;

a counter for counting clocks upon receipt of a count instruction signal; and

a control circuit for generating, upon receipt of said comparative output, said integral output voltage reduction signal and said count instruction signal, and wherein

said comparison circuit has

a first comparator for generating a first comparative output when said integral output voltage exceeds in absolute value a negative predetermined level;

a second comparator for generating a second comparative output when said integral output voltage is substantially zero; and

a third comparator for generating a third comparative output when said integral output voltage exceeds a positive predetermined level,

said counter is an up-down counter that counts up said clocks upon receipt of an up-count instruction signal and counts down said clocks upon receipt of a down-count signal; and

said control circuit generates said integral output voltage reduction signal and up-count instruction signal during a period which begins with the generation of said first comparative output and ends with the generation of said second comparative output, and generates said integral output voltage reduction signal and said down-count instruction signal during a period which begins with the generation of said third comparative output and ends with the generation of said second comparative output.

3. An integration type AID conversion method, comprising:

a first step of integrating an input signal to generate an integral output voltage;

a second step of comparing said integral output voltage with a predetermined value to generate a comparative output;

a third step of generating an integral output voltage reduction signal and a count instruction signal upon receipt of said comparative signal;

a fourth step of bringing said integral output voltage back to the initial level thereof by a predetermined magnitude per unit time upon receipt of said integral output voltage reduction signal; and

a fifth step of counting clocks upon receipt of said count instruction signal to output the counts of clocks counted, and wherein

in said second step, a first comparative output is generated when said integral output voltage exceeds in absolute value a negative predetermined level;

a second comparative output is generated when said integral output voltage is substantially zero; and

a third comparative output is generated when said integral output voltage exceeds a positive predetermined positive level;

in said third step, said integral output voltage reduction signal and said up-count instruction signal are generated during a period which begins with the generation of said first comparative output and ends with the generation of said second comparative output, and

said integral output voltage reduction signal and said down-count instruction signal are generated during a period which begins with the generation of said third comparative output and ends with the generation of said second comparative output.