Electro-optical device and method of driving the same

• US 6,693,681 B1
• Filed: 05/29/1998
• Issued: 02/17/2004
• Est. Priority Date: 04/28/1992
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko
• Primary Examiner(s): Chowdhury, Tarifur R.
• Assistant Examiner(s): DUONG, TAI V
• Application Number:
  US09/086,720
• Time in Patent Office: 2,090 Days
• Field of Search: 349/38, 349/139, 349/43, 349/122, 349/187, 349/39, 349/143, 257/59, 257/72, 345/92
• US Class Current: 349/38
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

An active matrix display device for suppressing voltage variation ΔV due to off-operation of a gate pulse, including TFTs and picture-element electrodes, at least one of the TFTs being assigned to each picture element, and each of the TFTs having a gate electrode connected to a gate line (first gate line), and a source and a drain one of which is connected to a data line, wherein a picture-element electrode concerned is formed so as to be overlapped with the first gate line through an insulator, and also so as to be overlapped through an insulator with a gate line other than the first gate line or a wiring disposed in parallel to the first gate line.

Claims

1. An active matrix device comprising:

a plurality of inverted stagger type thin film transistors formed on an insulating surface, each of the inverted stagger type thin film transistors having;

a gate electrode comprising aluminum,

a gate insulating film formed over said gate electrode,

an amorphous semiconductor film comprising silicon and being formed on the gate insulating film;

a channel region formed in the amorphous semiconductor film;

a source region in contact with the channel region;

a drain region in contact with the channel region;

a plurality of gate lines and a plurality of data lines provided over said insulating surface in an intersecting relation via an insulating film, each of said gate lines being connected to the gate electrode wherein each of the plurality of gate lines comprises aluminum;

a plurality of pixel electrodes electrically connected to one of said source and drain regions and arranged in a plurality of regions surrounded with the gate and data lines, respectively; and

a leveling film to provide a leveled upper surface and to isolate said pixel electrodes from said gate and data lines,

wherein each of said plurality of pixel electrodes overlaps one of said plurality of gate lines to form at first capacitance and another one of said plurality of gate lines to form a second capacitance and said first capacitance is equal to the second capacitance.

2. A device according to claim 1, wherein said leveling film comprises an organic material.

3. An active matrix device comprising:

a plurality of inverted stagger type thin film transistors formed on an insulating surface, each of the inverted stagger type thin film transistors having;

a gate electrode,

a gate insulating film on the gate electrode,

an amorphous semiconductor film comprising silicon and formed on the gate insulating film;

a channel region formed in the amorphous semiconductor film;

a source region in contact with the channel region;

a drain region in contact with the channel region;

a plurality of gate lines and a plurality of data lines provided over the insulating surface in an intersecting relation via an insulating film, each of said gate lines connected to the gate electrode;

a plurality of pixel electrodes electrically connected to one of the source and drain regions; and

a leveling film formed over the plurality of inverted stagger thin film transistors, the plurality of data lines and the plurality of gate lines,

wherein the plurality of the pixel electrodes are formed in a self-alignment manner with respect to the plurality of gate lines, the gate electrode, and the plurality of data lines with said plurality of gate lines, the gate electrode and said plurality of data lines used as a mask in an exposure of a resist for patterning said plurality of pixel electrodes,

wherein the periphery of each of the plurality of pixel electrodes overlaps the plurality of gate lines and the plurality of data lines with the leveling film therebetween, and

wherein each of the pixel electrodes overlaps one of the plurality of gate lines to form a first capacitance and another one of the plurality of gate lines to form a second capacitance and said first capacitance is equal to the second capacitance.

4. A device according to claim 3, wherein the leveling film comprises an organic material.

5. A device according to claim 3, wherein each of the plurality of pixel electrodes is transparent.

6. An active matrix device comprising:

a plurality of inverted stagger type thin film transistors formed on an insulating surface, each of the inverted stagger type thin film transistors having;

a gate electrode,

a gate insulating film on the gate electrode,

an amorphous semiconductor film comprising silicon and formed on the gate insulating film;

a channel region formed in the amorphous semiconductor film;

a source region in contact with the channel region;

a drain region in contact with the channel region;

a plurality of gate lines and a plurality of data lines provided over the insulating surface in an intersecting relation via an insulating film, each of said gate lines connected to the gate electrode;

a plurality of pixel electrodes electrically connected to one of the source and drain regions; and

a second insulating film formed over the plurality of inverted stagger thin film transistors, the plurality of data lines and the plurality of gate lines,

wherein the plurality of the pixel electrodes are formed in a self-alignment manner at least with respect to the plurality of gate lines and the gate electrode using at least said plurality of gate lines and the gate electrode used as a mask in an exposure of resist for patterning the pixel electrodes,

wherein each of the pixel electrodes overlaps one of the plurality of gate lines to form a first capacitance and another one of the plurality of gate lines to form a second capacitance and said first capacitance is equal to the second capacitance.

7. A device according to claim 6, wherein the second insulating film comprises an organic material.

8. A device according to claim 6, wherein each of the plurality of pixel electrodes is transparent.

9. An active matrix device comprising:

a plurality of data lines arranged over an insulating surface;

a plurality of gate lines over the insulating surface;

a plurality of inverted stagger type thin film transistors over the insulating surface, the inverted stagger type thin film transistor comprising;

a gate electrode electrically connected with one of the plurality of gate lines,

a gate insulating film on the gate electrode,

an amorphous semiconductor film comprising silicon and formed on the gate insulating film,

a channel region formed in the amorphous semiconductor film;

a source region in contact with the channel region;

a drain region in contact with the channel region;

a leveling film comprising an organic material and formed over the source and the drain regions;

a plurality of pixel electrodes formed on the leveling film;

wherein one of the source and the drain regions is electrically connected with one of the plurality of data lines and the other of the source and the drain regions is electrically connected with the pixel electrode,

wherein a periphery of the pixel electrode is substantially coextensive with an edge of one of the gate lines associated with said pixel electrode, an edge of the gate electrode connected to said one of the gate lines and an edge of another one of the gate lines, and

wherein each of the pixel electrodes overlaps one of the plurality of gate lines to form a first capacitance and another one of the plurality of gate lines to form a second capacitance and said first capacitance is equal to the second capacitance.

10. A device according to claim 9, wherein the organic material comprises polyimide.

11. A device according to claim 9, wherein each of the plurality of pixel electrodes is transparent.

12. An active matrix device comprising:

at least first and second data lines arranged over an insulating surface;

at least first and second gate lines over the insulating surface;

at least an inverted stagger type thin film transistor surrounded with the first and the second data lines and the first and the second gate lines, the inverted stagger type thin film transistor comprising;

a gate electrode electrically connected with the first gate line,

a gate insulating film on the gate electrode,

an amorphous semiconductor film comprising silicon and formed on the gate insulating film,

a channel region formed in the amorphous semiconductor film;

a source region in contact with the channel region;

a drain region in contact with the channel region;

an insulating film formed over the source and the drain regions;

a pixel electrode formed on the leveling film;

wherein one of the source and the drain regions is electrically connected with the first data line and the other is electrically connected with the pixel electrode,

wherein a periphery of the pixel electrode overlaps with the first and the second gate lines, and wherein said pixel electrode is formed by using at least said first and second gate lines and said gate electrode as a mask in an exposure of a resist for patterning said pixel electrode, and

wherein a first capacitance formed between said pixel electrode and said first gate line is the same as a second capacitance formed between said pixel electrode and said second gate line.

13. A device according to claim 12, wherein the insulating film comprises an organic material.

14. A device according to claim 13, wherein the organic material comprises polyimide.

15. A device according to claim 12, wherein the pixel electrode is transparent.

16. An active matrix device comprising:

at least first and second data lines arranged over an insulating surface;

at least first and second gate lines over the insulating surface;

at least an inverted stagger type thin film transistor surrounded with the first and the second data lines and the first and the second gate lines, the inverted stagger type thin film transistor comprising;

a gate electrode electrically connected with the first gate line and comprising aluminum,

a gate insulating film on the gate electrode,

an amorphous semiconductor film comprising silicon and formed on the gate insulating film,

a channel region formed in the amorphous semiconductor film;

a source region in contact with the channel region;

a drain region in contact with the channel region;

an insulating film formed over the source and the drain regions;

a pixel electrode formed on the leveling film;

wherein one of the source and the drain regions is electrically connected with the first data line and the other is electrically connected with the pixel electrode,

wherein a periphery of the pixel electrode overlaps with the first and second gate lines, and wherein a first capacitance formed between said pixel electrode and said first gate line is the same as a second capacitance formed between said pixel electrode and said second gate line.

17. A device according to claim 16, wherein the insulating film comprises polyimide.

18. A device according to claim 16, wherein the pixel electrode is transparent.