Surge suppression for current limiting circuits

• US 6,693,782 B1
• Filed: 09/20/2000
• Issued: 02/17/2004
• Est. Priority Date: 09/20/2000
• Status: Expired due to Term

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Lash, Steven J.
• Primary Examiner(s): Sircus, Brian
• Assistant Examiner(s): Rodriguez, Isabel
• Application Number:
  US09/667,394
• Time in Patent Office: 1,245 Days
• Field of Search: 361/93.9, 361/57, 361/87
• US Class Current: 361/93.9
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H02J 7/00302 Overcharge protection
• CPC Class Codes: H02J 7/00304 Overcurrent protection
• CPC Class Codes: H02J 7/00711 with introduction of pulses during the charging process
• CPC Class Codes: H02J 7/00714 in response to battery charging or discharging current

Abstract

A limiting circuit for controlling overshoot in a charge current in a battery recharging system includes a current amplifier receiving input indicative of charge current in a rechargeable battery circuit and generating a current error signal, a voltage amplifier receiving input indicative of charge voltage in the rechargeable battery circuit and generating a voltage error signal, and a power amplifier receiving a first signal indicative of power in a switching voltage regulator and a second power signal indicative of power in the rechargeable battery circuit, and generating a power error signal. The limiting circuit compares the voltage error signal, the current error signal, and the power error signal to determine the error signal having the greatest value, and generates an input signal to a pulse width modulation comparator. The limiting circuit also includes an internal current source, a first transistor coupled to the current amplifier, a second transistor coupled to the voltage amplifier; and a third transistor coupled to the power amplifier. The first transistor, the second transistor, and the third transistor are coupled to the internal current source to determine the error signal having the greatest value. To prevent reverse current flow in the switching voltage regulator, a low current comparator receives a signal indicative of the current flowing in the switching voltage regulator, and generates an output signal. A transistor receives the output signal from the low current comparator, and generates a signal to maintain the current flowing in the switching regulator circuit above a threshold value.

Claims

1. A surge protection circuit for protecting volatile electronic components from data loss comprising:

a current limiter having an input voltage coupled to an input supply voltage to a peripheral and the current limiter having an output voltage;

a current source coupled to the input supply voltage providing an additional source of current for a limited period of time such that the input voltage does not fall below a level causing volatile data to be lost; and

a current rate limiting circuit reducing the rate of flow of current to the peripheral device and having a first terminal coupled to the output voltage of the current limiter and the current rate limiting circuit having a second terminal available as an output load voltage such that the rate of flow of current is inversely proportional to the additional source of current during a loop response time.

2. The surge protection circuit of claim 1, wherein the current limiter is a commercially available integrated circuit device.

3. The surge protection circuit of claim 1, wherein the current source is a capacitor and the current rate limiting circuit is an inductor, such that the size of the capacitor is inversely proportional to the size of the inductor.

4. The surge protection circuit of claim 1, further comprising:

a first clamping diode having a first terminal coupled to the first terminal of the current rate limiting circuit and the clamping diode having a second terminal coupled to the input supply voltage; and

a second clamping diode having a first terminal coupled to the first terminal of the current rate limiting circuit and the second clamping diode having a second terminal coupled to ground.

5. A method of suppressing current surges comprising:

providing a source of current to a load from an input supply voltage to a peripheral;

limiting the source of current and reducing the rate of flow of current from the input supply voltage provided to the load to a set output current level such that when the source of current from the input supply voltage exceeds the set output current level the source of current from the input supply voltage is limited to the set output current level after a loop response time;

opposing a rapid change in the rate of flow of current from the input supply voltage to the load; and

providing an additional source of current to the load for a limited period of time such that the provision of the source of current to the load from the input supply voltage during the rapid change in the rate of flow of current does not cause the input supply voltage to drop below a minimum necessary voltage level to prevent data loss in volatile electronic components such that the rate of flow of current is inversely proportional to the additional source of current during the loop response time.

6. A computer system having a surge protection circuit for protecting volatile electronic components from data loss due to voltage variances, the computer system comprising:

a system bus;

at least one microprocessor connected to access the system bus;

one or more peripherals, each connected to access the system bus;

a means for attaching one or more additional peripherals to access the system bus wherein a peripheral load voltage is supplied to the one or more additional peripherals;

a power supply for supplying an input supply voltage to the computer system;

a surge protection circuit for preventing the input supply voltage from dropping to a level which causes volatile data to be lost when attaching the one or more additional peripherals to the system bus comprising;

a current limiter having an input voltage coupled to the input supply voltage and the current limiter having an output voltage;

a current source coupled to the input supply voltage providing an additional source of current for a limited period of time such that the input supply voltage does not fall below a level causing volatile data to be lost; and

a current rate limiting circuit reducing the rate of flow of current to a peripheral device and having a first terminal coupled to the output voltage of the current limiter and the current rate limiting circuit having a second terminal connected to the peripheral load voltage such that the rate of flow of current is inversely proportional to the additional source of current during a loop response time.

7. The computer system of claim 6, wherein the current limiter is a commercially available integrated circuit device.

8. The computer system of claim 6, wherein the current source is a capacitor and the current rate limiting circuit is an inductor, such that the size of the capacitor is inversely proportional to the size of the inductor.

9. The computer system of claim 6, further comprising:

a first clamping diode having a first terminal coupled to the first terminal of the current rate limiting circuit and the clamping diode having a second terminal coupled to the input supply voltage; and

a second clamping diode having a first terminal coupled to the first terminal of the current rate limiting circuit and the second clamping diode having a second terminal coupled to ground.