Fast acquisition module for a code division multiple access (CDMA) wireless local loop (WLL) system

• US 6,693,890 B1
• Filed: 06/14/2000
• Issued: 02/17/2004
• Est. Priority Date: 03/03/2000
• Status: Expired due to Fees

• Current Assignee: Mr Cruise, Ian Gerard
• Original Assignee: Carlson Wireless Incorporated
• Inventors: Flores, Christopher, Ross, Ronald, Yick, Karl, Correya, Oswald
• Primary Examiner(s): Yao, Kwang Bin
• Application Number:
  US09/594,468
• Time in Patent Office: 1,343 Days
• Field of Search: 370/321, 370/335, 370/342, 370/503, 370/509, 370/510, 370/512, 370/513, 370/514, 370/515, 375/130, 375/134, 375/136, 375/137, 375/140, 375/143, 375/145, 375/147, 375/149, 375/152
• US Class Current: 370/342
• CPC Class Codes: H04B 1/70752 Partial correlation
• CPC Class Codes: H04B 1/70775 Multi-dwell schemes, i.e. multiple accumulation times

Abstract

An acquisition module for acquiring signal timing in a CDMA system has a register for storing and organizing synchronization code, at least 4 match filters for match filtering between I/Q samples and the corresponding synchronization code, at least 4 absolute value blocks for determining absolute values of match filtering results, a summation function for summing results obtained through match filtering and through absolute value taking, and a control logic for controlling the acquisition process, characterized in that the acquisition module loads a 64-bit section of synchronization code and I/Q complex samples and match filters them in a simultaneous manner and, upon registering a value greater than a preset threshold, acquires an initial timing, the initial timing being verified over the remaining 64-bit sections of synchronization code using the same control circuitry used in acquiring the timing.

Claims

1. An acquisition module for acquiring signal timing in a CDMA system comprising:

a register for storing and organizing synchronization code;

at least 4 match filters for match filtering between I/Q samples and the corresponding synchronization code;

at least 4 absolute value blocks for determining absolute values of match filtering results;

a summation function for summing results obtained through match filtering and through absolute value taking; and

a control logic for controlling the acquisition process;

characterized in that the acquisition module loads a 64-bit section of synchronization code and I/Q complex samples and match filters them in a simultaneous manner and, upon registering a value greater than a preset threshold, acquires an initial timing, the initial timing being verified over the remaining 64-bit sections of synchronization code using the same control circuitry used in acquiring the timing.

2. The acquisition module of claim 1, wherein both small and large phase error samples are computed using the same control circuitry.

3. The acquisition module of claim 2, wherein match filtering is performed at ½

chip intervals.

4. The acquisition module of claim 3, wherein during the initial verification performed on the first 64-bits of code after acquisition, a fine tuning operation is performed by checking for a better peak correlation at ½

-chip offset positions over a duration of 1.5 chips.

5. A method for acquiring signal timing for a CDMA system comprising the steps of:

a) loading a 64-bit section of synchronization code into an acquisition module;

b) receiving 64 bits of I/Q complex samples corresponding to the 64-bit section of synchronization code;

c) match filtering the synchronization code and the I/Q complex samples simultaneously using at least 4 16-bit match filters;

d) comparing match filtering results with a preset threshold; and

e) depending upon the comparison, determining whether a received signal timing is acceptable for acquisition and verification.

6. The method of claim 5 wherein in step e), a first comparison of match-filtering results with a preset threshold determines whether or not an initial timing will be acquired, and subsequent comparisons determined whether or not an acquired signal timing will be verified.

7. The method of claim 6 wherein in step (c), both small and large phase error samples are computed using the same control circuitry.

8. The method of claim 7 wherein in step (c), match filtering is performed at ½

chip intervals.

9. The method of claim 8 wherein in step (c), during the initial verification performed on the first 64-bits of code after acquisition, a fine tuning operation is performed by checking for a better peak correlation at ½

-chip offset positions over a duration of 1.5 chips.