Digital-to-analog DAC-driven phase-locked loop PLL with slave PLL's driving DAC reference voltages

• US 6,693,987 B1
• Filed: 10/05/2000
• Issued: 02/17/2004
• Est. Priority Date: 10/05/2000
• Status: Expired due to Fees

• Current Assignee: Celanese Acetate LLC (Celanese Corporation), Diodes Incorporated
• Original Assignee: Pericom Semiconductor Corporation (Diodes Incorporated)
• Inventors: Hattori, Hide
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US09/679,682
• Time in Patent Office: 1,230 Days
• Field of Search: 375/215, 375/294, 375/327, 375/373, 375/374, 375/375, 375/376, 327/55, 327/58, 327/68, 327/90, 327/3, 327/5, 327/16, 327/37, 327/40, 327/147, 327/156, 327/157, 329/306, 329/307, 329/359, 329/358, 329/360, 331/25, 331/2, 331/11
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A clock generator uses two PLL loops and a digital-to-analog converter (DAC) to generate a variable output frequency from a single fixed-frequency reference clock. Each PLL loop receives the reference clock and phase-compares it with a feedback clock. The feedback clock in one loop is slightly faster in frequency than the feedback clock in the second loop. The input voltages to voltage-controlled oscillators (VCOs) in the two loops thus vary slightly. A DAC is connected between the two VCO inputs. The DAC'"'"'s two reference-voltage inputs are connected to these VCO inputs. The DAC'"'"'s output voltage is selected from within the voltage range between the two VCO voltages by a digital code-word input to the DAC. The DAC'"'"'s output voltage is input to a final VCO that generates the variable output frequency. The output frequency is varied by selecting the digital code-word input to the DAC.

Claims

1. A dual-loop digitally-tuned clock generator comprising:

a reference-clock input, having a reference frequency;

a first phase-locked loop, receiving the reference-clock input, for generating a first feedback clock having a first feedback frequency, the first phase-locked loop phase comparing the reference-clock input to the first feedback clock, the first phase-locked loop charging and discharging a first capacitance in response to phase comparison to adjust a first voltage;

a second phase-locked loop, receiving the reference-clock input, for generating a second feedback clock having a second feedback frequency, the second phase-locked loop phase comparing the reference-clock input to the second feedback clock, the second phase-locked loop charging and discharging a second capacitance in response to phase comparison to adjust a second voltage;

wherein the second voltage differs from the first voltage;

a digital-to-analog converter (DAC) coupled between the first voltage and the second voltage, the DAC for generating a selectable voltage, wherein the selectable voltage is a voltage between the first voltage and the second voltage, the selectable voltage being selectable by a digital select input to the DAC; and

an output-clock generator, coupled to the DAC by selectable voltage, for generating an output clock having an output frequency, the output frequency determined by the selectable voltage,

whereby the output frequency is determined by the selectable voltage of the DAC coupled between the first and second phase-locked loops.

2. The dual-loop digitally-tuned clock generator of claim 1 wherein the first phase-locked loop has a first voltage-controlled oscillator (VCO) that receives the first voltage, the first VCO generating a first clock having a first frequency;

wherein the second phase-locked loop has a second VCO that receives the second voltage, the second VCO generating a second clock having a second frequency;

whereby the first and second phase-locked loops use VCOs to generate clocks.

3. The dual-loop digitally-tuned clock generator of claim 2 wherein the output frequency is selectable between the first frequency and the second frequency,

whereby the output frequency is an intermediate frequency.

4. The dual-loop digitally-tuned clock generator of claim 2 wherein the first phase-locked loop further has a first divider, coupled to an output of the first VCO, for dividing the first frequency to generate the first feedback clock;

wherein the second phase-locked loop further has a second divider, coupled to an output of the second VCO, for dividing the second frequency to generate the second feedback clock,

whereby dividers generate feedback clocks.

5. The dual-loop digitally-tuned clock generator of claim 4 wherein the second divider divides by a larger divisor than the first divider,

whereby different feedback divisors are used by the first and second phase-locked loops.

6. The dual-loop digitally-tuned clock generator of claim 2 wherein the output-clock generator is a third VCO that generates the output clock with the output frequency being a function of the selectable voltage,

whereby the output clock is generated by the third VCO.

7. The dual-loop digitally-tuned clock generator of claim 6 wherein the DAC further comprises:

maximum reference-voltage input, coupled to the first voltage from the first phase-locked loop;

a minimum reference-voltage input, coupled to the second voltage from the second phase-locked loop;

whereby the DAC generates the selectable voltage from the first and second voltages.

8. The dual-loop digitally-tuned clock generator of claim 7 wherein the selectable voltage is selected from a plurality of voltages generated by the DAC, the plurality of voltages being separated by equal voltage intervals,

whereby the selectable voltage of the DAC is selected from equally divided voltage intervals by the DAC.

9. The dual-loop digitally-tuned clock generator of claim 8 wherein the output frequency is selected as a linear function having endpoints determined by the first and second frequencies.

10. The dual-loop digitally-tuned clock generator of claim 9 further comprising:

an input divider, receiving a primary-input clock, for dividing the primary-input clock to generate the reference-clock input having the reference frequency,

whereby the primary-input clock is divided.

11. The dual-loop digitally-tuned clock generator of claim 10 wherein the first phase-locked loop further comprises a first charge pump, responsive to phase comparison by the first phase-locked loop, for charging and discharging the first capacitance;

wherein the second phase-locked loop further comprises a second charge pump, responsive to phase comparison by the second phase-locked loop, for charging and discharging the second capacitance.

12. The dual-loop digitally-tuned clock generator of claim 11 wherein the first capacitance is in a first low-pass filter that has a first resistance, and the second capacitance is in a second low-pass filter that has a second resistance.

13. A dual phase-locked loop (PLL) variable-frequency clock generator comprising:

a fixed-frequency clock input;

a first PLL, receiving the fixed-frequency clock input, for generating a first voltage on a first node, the first voltage determining a first frequency of the first PLL;

a second PLL, receiving the fixed-frequency clock input, for generating a second voltage on a second node, the second voltage determining a second frequency of the second PLL;

a digital-to-analog converter (DAC), coupled between the first and second PLL, connected to the first node at a first reference-voltage terminal of the DAC, and connected to the second node at a second reference-voltage terminal of the DAC, the DAC for selecting a final voltage from voltages between the first voltage and the second voltage;

a final voltage-controlled oscillator (VCO), receiving the final voltage from the DAC, for generating a final clock having a final frequency that is determined by the final voltage input to the final VCO; and

whereby the final frequency is selectable by the DAC that generates the final voltage between the first and second voltages generated as DAC reference voltages by the first and second PLL'"'"'s.

14. The dual PLL variable-frequency clock generator of claim 13 wherein the first PLL comprises:

a first phase comparator, receiving the fixed-frequency clock input and a first feedback clock, for comparing phases of the fixed-frequency clock and the first feedback clock;

a charge pump, responsive to the first phase comparator, for charging and discharging the first node in response to a phase difference between the fixed-frequency clock and the first feedback clock;

a first VCO, coupled to the first node, for generating a first clock having a first frequency determined by the first voltage;

a first feedback divider, receiving the first clock, for generating the first feedback clock;

wherein the second PLL comprises;

a second phase comparator, receiving the fixed-frequency clock input and a second feedback clock, for comparing phases of the fixed-frequency clock and the second feedback clock;

a charge pump, responsive to the second phase comparator, for charging and discharging the second node in response to a phase difference between the fixed-frequency clock and the second feedback clock;

a second VCO, coupled to the second node, for generating a second clock having a second frequency determined by the second voltage;

a second feedback divider, receiving the second clock, for generating the second feedback clock,

whereby the first and second VCO determine frequencies of the first and second clocks.

15. The dual PLL variable-frequency clock generator of claim 14 wherein the first PLL further comprises a first low-pass filter, coupled to the first node, for filtering phase differences among several clock periods;

wherein the second PLL further comprises a second low-pass filter, coupled to the second node, for filtering phase differences among several clock periods,

whereby low-pass filtering is performed.

16. The dual PLL variable-frequency clock generator of claim 15 wherein the second feedback divider divides the second clock by N, wherein N is a whole number, while the first feedback divider divides the first clock by N+R, wherein R is a whole number that is smaller than N,

whereby the first PLL divides by a larger number than the second PLL, causing the first voltage to be greater than the second voltage.

17. The dual PLL variable-frequency clock generator of claim 16 wherein the DAC receives an K-bit digital input, wherein K is a whole number, the DAC for dividing a voltage range between the first voltage and second voltage into a plurality of 2^K−

1 voltage intervals, the DAC selecting a voltage from among the voltage intervals in response to the K-bit digital input.

18. A variable-frequency clock generator comprising:

clock input means for receiving a reference clock having a reference frequency;

first loop means, receiving the reference clock, for locking a first feedback clock to the reference clock by adjusting a first voltage of a first node;

second loop means, receiving the reference clock, for locking a second feedback clock to the reference clock by adjusting a second voltage of a second node;

wherein the first and second voltage are not equal in voltage;

digital-to-analog converter (DAC) means, having a digital input, a first analog voltage input coupled to the first node, and a second analog voltage input coupled to the second node, for converting the digital input into one of a plurality of different voltages having values from the first voltage to the second voltage, the DAC generating as an output voltage one of the plurality of different voltages in response to the digital input; and

output clock means, responsive to the DAC means, for generating an output clock having an output frequency that is determined by the output voltage generated by the DAC means,

whereby the output frequency is determined by the DAC means and the first and second loop means.

19. The variable-frequency clock generator, of claim 18 wherein the output clock means comprises voltage-controlled oscillator (VCO) means for converting the output voltage to the output clock having the output frequency being a predetermined function of the output voltage.

20. The variable-frequency clock generator of claim 19 wherein the first loop means comprises:

first phase compare means, receiving the reference clock and the first feedback clock, for comparing clock phases;

first charge means, responsive to a phase difference from the first phase compare means, for increasing and decreasing the first voltage;

first VCO means, responsive to the first voltage, for generating a first clock with a first frequency being a predetermined function of the first voltage;

first feedback divider means, receiving the first clock, for generating the first feedback clock;

wherein the second loop means comprises;

second phase compare means, receiving the reference clock and the second feedback clock, for comparing clock phases;

second charge means, responsive to a phase difference from the second phase compare means, for increasing and decreasing the second voltage;

second VCO means, responsive to the second voltage, for generating a second clock with a second frequency being a predetermined function of the second voltage;

second feedback divider means, receiving the second clock, for generating the second feedback clock;

wherein the first and second feedback divider means divide by different values.