Multi-mode network interface having loadable software images

• US 6,694,360 B1
• Filed: 06/09/2000
• Issued: 02/17/2004
• Est. Priority Date: 06/09/2000
• Status: Expired due to Term

• Current Assignee: Valtrus Innovations Limited (f/k/a Dolya Holdco 9 Limited) (Key Patent Innovations Limited)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Pickreign, Heidi R., Krishnamurthy, Laxminarayan, Duguay, Christopher J., Cross, Patricia C.
• Primary Examiner(s): Kincaid, Kristine
• Assistant Examiner(s): Narayanaswamy, Sindya
• Application Number:
  US09/591,568
• Time in Patent Office: 1,348 Days
• Field of Search: 709/220-225, 709/317, 709/202
• US Class Current: 709/220
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A multi-mode network interface adapter includes a diagnostic mode, a sleep mode and a run-time mode. The network adapter enters the diagnostic mode at least in response to a power-up signal and validates the operation of predetermined network adapter functions. In the sleep mode, the network adapter transmits messages onto the network and responds to messages received from the network that would otherwise be handled by a host computer operating system. In this mode, the network adapter creates the appearance to other devices that the host computer is operational even if the host computer has entered a reduced power state in which the host computer operating system is not operational. In the run-time mode, the network adapter passes messages received from the network to the host computer and transmits messages received from the host computer over the network.

Claims

1. A multi-mode network adapter comprising:

at least one processor;

at least one memory; and

at least one program storage configured to store at least a first program, a second program, and a third program,

wherein said network adapter is operative to load one or more of the programs from the program storage to the memory for subsequent execution by the processor,

wherein said processor is operative to executer the first program out of said memory in response to a first predetermined condition to test predetermined functions associated with said network adapter,

wherein said processor is operative to execute the second program out of said memory in response to a second predetermined condition to respond to at least one network message received by said network adapter over a network when a host computer in electrical communication with said network adapter is in a reduced power state in which a host operating system within said host computer is not operational, and

wherein said processor is operative to execute the third program out of said memory in response to a third predetermined condition to forward messages received over said network to said host computer and to forward messages received from said host computer onto said network.

2. The multi-mode network adapter of claim 1 further including a first plurality of registers for forwarding messages from the processor to the host computer, and a second plurality of registers for receiving messages from the host computer at the processor.

3. The multi-mode network adapter of claim 2 wherein the processor is further operative to download the third program from the host computer to the at least one memory using at least the second plurality of registers.

4. The multi-mode network adapter of claim 1 wherein the processor is further operative to download the third program from the host computer to the at least one memory using a DMA interface included in the host computer.

5. The multi-mode network adapter of claim 1 wherein the processor and the host computer are communicably coupled via a PCI bus.

6. A method of operating a multi-mode network adapter including at least one processor and at least one memory, the method comprising the steps of:

storing at least a first program, a second program, and a third program in at least one program storage, the program storage being included in the network adapter;

loading one or more of the programs from the program storage to the memory for subsequent execution by the processor;

executing the first program out of the memory in response to a first predetermined condition to test predetermined functions associated with the network adapter;

executing the second program out of the memory in response to a second predetermined condition to respond to at least one network message received by the network adapter over a network when a host computer in electrical communication with the network adapter is in a reduced power state in which a host operating system within the host computer is not operational; and

executing the third program out of the memory in response to a third predetermined condition to forward messages received over the network to the host computer and to forward messages received from the host computer onto the network.

7. The method of claim 6 further including the steps of, while executing at least the third program, forwarding messages from the processor to the host computer using a first plurality of registers, and receiving messages from the host computer at the processor using a second plurality of registers.

8. The method of claim 7 further including the step of downloading the third program from the host computer to the at least one memory using at least the second plurality of registers.

9. The method of claim 6 further including the step of downloading the third program from the host computer to the at least one memory using a DMA interface included in the host computer.

10. The method of claim 7 further including the step of executing a fourth program out of the at least one memory in response to a fourth predetermined condition to test predetermined functions associated with the first and second pluralities of registers.

11. The method of claim 10 wherein, while testing the predetermined functions associated with the first plurality of registers, receiving messages from the host computer at the processor using the second plurality of registers to confirm test results.

12. The method of claim 10 wherein, while testing the predetermined functions associated with the second plurality of registers, forwarding messages from the processor to the host computer using the first plurality of registers to initialize test conditions.