Mapping requests from a processing unit that uses memory-mapped input-output space
First Claim
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1. A method of performing a request from a central processing unit that uses memory-mapped input-output space, the method comprising:
- converting a request directed to the input-output space of the central processing unit to a corresponding command that simulates an operation between components in a second processing domain;
executing the command in the second processing domain, wherein the second processing domain comprises a multithreaded processing domain, and wherein the multithreaded domain includes micro-coded processing engines that support multiple threads, the threads are simultaneously active but only one thread is in operation at any one time; and
accessing information according to the request in response to executing the command.
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Abstract
A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.
231 Citations
27 Claims
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1. A method of performing a request from a central processing unit that uses memory-mapped input-output space, the method comprising:
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converting a request directed to the input-output space of the central processing unit to a corresponding command that simulates an operation between components in a second processing domain;
executing the command in the second processing domain, wherein the second processing domain comprises a multithreaded processing domain, and wherein the multithreaded domain includes micro-coded processing engines that support multiple threads, the threads are simultaneously active but only one thread is in operation at any one time; and
accessing information according to the request in response to executing the command. - View Dependent Claims (2)
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3. A method of writing information from a central processing unit that uses memory-mapped input-output space, the method comprising:
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sending a request from the central processing unit to an address in the input-output space, wherein the address is associated with a destination in an bus interface unit;
converting the address and a command type associated with the request to a corresponding command having a format used for communications between an engine in the bus interface unit and one or more micro-coded processing engines, wherein the micro-coded processing engines support multiple threads, the threads are simultaneously active but only one thread is in operation at any one time;
executing the command in the engine in the bus interface unit; and
writing the information to the destination in the bus interface unit in response to executing the command. - View Dependent Claims (4, 5)
causing a control signal to be sent from the engine in the bus interface unit; and
promoting the information, in response to the control signal, onto a bus used for communications between the bus interface unit and the one or more micro-coded processing engines.
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5. The method of claim 4 including giving the command a higher priority than commands from the one or more micro-coded processing engines.
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6. A method of writing information from a central processing unit that uses memory-mapped input-output space, the method comprising:
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sending a request from the central processing unit to an address in the input-output space, wherein the address is associated with a destination in a micro-coded processing engine;
converting the address and a command type associated with the request to a corresponding command in a format used for communications between an engine in a bus interface unit and the micro-coded processing engine, wherein micro-coded processing engine supports multiple threads, the threads are simultaneously active but only one thread is in operation at any one time;
executing the command in the engine in the bus interface unit; and
writing the information to the destination in the micro-coded processing engine in response to executing the command. - View Dependent Claims (7, 8, 9)
causing a control signal to be asserted by the engine in the bus interface unit; and
promoting the information, in response to the control signal, onto a bus used for communications between the bus interface unit and the micro-coded processing engine.
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8. The method of claim 7 including:
causing the engine in the bus interface unit to assert address signals on a bus used for communications between the bus interface unit and the micro-coded processing engine, wherein the asserted address signals enable the micro-coded processing engine to accept the information.
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9. The method of claim 7 including giving the command a higher priority than commands from the micro-coded processing engine.
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10. A method of providing information from a bus interface unit to a central processing unit that uses memory-mapped input-output space, the method comprising:
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sending a request from the central processing unit to an address in the input-output space, wherein the address is associated with a location in the bus interface unit;
converting the address and a command type associated with the request to a corresponding command having a format used for communications between an engine in the bus interface unit and one or more micro-coded processing engines, wherein the micro-coded processing engines support multiple threads, the threads are simultaneously active but only one thread is in operation at any one time;
executing the command in the engine in the bus interface unit; and
providing the information to the central processing unit in response to executing the command. - View Dependent Claims (11, 12, 13)
promoting the information from the location in the bus interface unit onto a first bus used for communications between the bus interface unit and the one or more micro-coded processing engines.
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12. The method of claim 11 including:
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causing a control signal to be asserted by the engine in the bus interface unit; and
promoting the information, in response to the control signal, from the first bus to a second bus coupled to the central processing unit.
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13. The method of claim 11 including giving the command a higher priority than commands from the one or more micro-coded processing engines.
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14. A method of providing information from a micro-coded processing engine to a central processing unit that uses memory-mapped input-output space, the method comprising:
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sending a request from the central processing unit to an address in the input-output space, wherein the address is associated with a location in the micro-coded processing engine;
converting the address and a command type associated with the request to a corresponding command having a format used for communications between an engine in a bus interface unit and the micro-coded processing engine, wherein the micro-coded processing engine supports multiple threads, the threads are simultaneously active but only one thread is in operation at any one time;
executing the command in the engine in the bus interface unit; and
providing the information to the central processing unit in response to executing the command. - View Dependent Claims (15, 16, 17)
promoting the information from the location in the micro-coded processing engine onto a first bus used for communications between the bus interface unit and the micro-coded processing engine.
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16. The method of claim 15 including:
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causing a control signal to be asserted by the engine in the bus interface unit; and
promoting the information, in response to the control signal, from the first bus to a second bus coupled to the central processing unit.
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17. The method of claim 15 including giving the command a higher priority than commands from the micro-coded processing engine.
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18. A parallel hardware-based multithreaded processor comprising:
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a central processing unit that coordinates system functions and that uses memory-mapped input-output space;
micro-coded processing engines that support multiple threads, the threads are simultaneously active but only one thread is in operation at any one time;
a bus interface unit;
a first bus coupled to the central processing unit; and
a second bus coupled to the micro-coded processing engines; and
a translator unit coupled between the first bus and the second bus to convert a request that is addressed to the input-output space of the central processing unit to a corresponding command that simulates operations between the bus interface unit and the micro-coded processing units. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26)
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27. An article comprising a computer-readable medium which stores computer-executable instructions for causing a computer system to:
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convert a request addressed to input-output space of a central processing unit to a corresponding command that simulates an operation between components in a multithreaded processing domain, wherein the multithreaded processing domain includes micro-coded processing engines that support multiple threads, the threads are simultaneously active but only one thread is in operation at any one time;
execute the command in the multithreaded processing domain; and
cause information to be accessed according to the request in response to executing the command.
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Specification