Managing bus transaction dependencies
First Claim
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1. A system, comprising:
- a command dispatcher coupled to a command queue;
broadcast command control logic having;
a first detector coupled to the command queue and the command dispatcher to detect if the command queue is full;
first logic coupled to the first detector to dispatch a broadcast command from the command dispatcher to the command queue if the command queue is not full; and
second logic coupled to the first detector to respond to the requestor with a first delayed transaction response if the command queue is full;
dispatch timer logic having;
a second detector coupled to the command dispatcher to detect if a first command dispatched to the command queue by the command dispatcher has been responded to;
a timer coupled to the second detector; and
third logic coupled to the timer to issue a deferred response to the requestor if the timer expires before the first command has been responded to; and
lock read control logic having;
a third detector coupled to the command queue to detect if write data buffer space and command buffer space are available for use by an initial locked memory read transaction that is potentially within programmable attribute map space;
fourth logic coupled to the command dispatcher to dispatch the read transaction if the write data buffer space and command buffer space are available; and
fifth logic coupled to the command dispatcher to issue a second delayed transaction response to the requestor if the write data buffer space and command buffer space are not available.
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Abstract
A combination of techniques to prevent deadlocks and livelocks in a computer system having a dispatcher and multiple downstream command queues. In one embodiment, a broadcast transaction that requires simultaneously available space in all the affected downstream command queues becomes a delayed transaction, so that the command queues are reserved and other transactions are retried until the broadcast transaction is completed. In another embodiment, a bail-out timer is used to defer a transaction if the transaction does not complete within a predetermined time. In yet another embodiment, a locked transaction that potentially addresses memory space controlled by a programmable attribute map is handled as a delayed transaction if there is less than a predetermined amount of downstream buffer space available for the transaction.
115 Citations
3 Claims
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1. A system, comprising:
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a command dispatcher coupled to a command queue;
broadcast command control logic having;
a first detector coupled to the command queue and the command dispatcher to detect if the command queue is full;
first logic coupled to the first detector to dispatch a broadcast command from the command dispatcher to the command queue if the command queue is not full; and
second logic coupled to the first detector to respond to the requestor with a first delayed transaction response if the command queue is full;
dispatch timer logic having;
a second detector coupled to the command dispatcher to detect if a first command dispatched to the command queue by the command dispatcher has been responded to;
a timer coupled to the second detector; and
third logic coupled to the timer to issue a deferred response to the requestor if the timer expires before the first command has been responded to; and
lock read control logic having;
a third detector coupled to the command queue to detect if write data buffer space and command buffer space are available for use by an initial locked memory read transaction that is potentially within programmable attribute map space;
fourth logic coupled to the command dispatcher to dispatch the read transaction if the write data buffer space and command buffer space are available; and
fifth logic coupled to the command dispatcher to issue a second delayed transaction response to the requestor if the write data buffer space and command buffer space are not available. - View Dependent Claims (2, 3)
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Specification
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Current AssigneeIntel Corporation
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Original AssigneeIntel Corporation
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InventorsGarcia, Serafin E., Bogin, Zohar
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Primary Examiner(s)VO, TIM T
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Application NumberUS09/659,108Time in Patent Office1,254 DaysField of Search710/53, 710/200, 710/220, 710/240-244, 710/25, 710/104, 710/57US Class Current710/53CPC Class CodesG06F 13/24 using interrupt G06F13/32 t...G06F 13/385 for adaptation of a particu...
