Multiprocessor digital data processing system

• US 6,694,412 B2
• Filed: 09/28/2001
• Issued: 02/17/2004
• Est. Priority Date: 12/22/1987
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Goodman, Nathan, Frank, Steven J., Margulies, Benson I., Weber, Frederick D., Lee, Linda O., Burkhardt, Henry III
• Primary Examiner(s): Ellis, Kevin L.
• Application Number:
  US09/967,404
• Publication Number:
  US 20020078310A1
• Time in Patent Office: 872 Days
• Field of Search: 711/119, 711/130, 711/147, 711/148, 711/153, 711/170, 711/173
• US Class Current: 711/153
• CPC Class Codes: G06F 11/004 Error avoidance G06F11/07 and subgroups take precedence
• CPC Class Codes: G06F 11/0724 in a multiprocessor or a multi-core unit multiprocessors per se G06F15/80
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 12/1018 involving hashing techniques, e.g. inverted page tables
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/272 Cache only memory architecture [COMA]
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/3005 to perform operations for flow control
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 : Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/468 : Specific access rights for resources, e.g. using capability register
• CPC Class Codes: G06F 9/5016 : the resource being the memory
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: H04L 12/4637 : Interconnected ring systems
• CPC Class Codes: H04L 45/04 : Interdomain routing, e.g. hierarchical routing

Abstract

A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed to selectively broadcast data access requests, updates and transfers on the rings.

Claims

1. A processing system comprising:

a plurality of interconnected processing cells, each having at least one processor and at least one storage element operable as a cache;

wherein said storage elements are configured to form a distributed main memory;

wherein said system comprises a system virtual address space, and wherein access to individual data elements stored within said processing cells is by reference to a unique system virtual address associated with each datum; and

wherein a plurality of memory pages are distributed among said storage elements with a number of memory pages being simultaneously held in a plurality of said storage elements; and

access rights are defined on a subpage basis.

2. The system of claim 1, wherein each of said cells includes a cache directory corresponding to the storage element of the cell, each directory including a list of descriptors reflecting the identity and state of each datum stored in the corresponding storage element.

3. The system of claim 1, wherein storage in said storage elements is allocated on a page basis.

4. The system of claim 3, wherein each storage element stores data on a subpage basis.

5. A processing system comprising:

a plurality of interconnected processing cells, each having at least one processor and at least one storage element operable as a cache;

wherein said storage elements are configured to form a distributed main memory wherein said system comprises a system virtual address space, and wherein access to individual data elements stored within said processing cells is by reference to a unique system virtual address associated with each datum;

wherein a page of said system virtual address space is either entirely present within said system, or not present at all;

wherein when a page of system virtual address space is resident in said system, one or more storage elements allocates a page of storage to the page, and wherein each subpage of the page is stored in one or more of the storage elements with space allocated to the page.

6. A processing system comprising a plurality of interconnected processing cells that have at least one processor and at least one storage element operable as a cache, wherein:

said storage elements are configured to form a distributed main memory composed of a plurality of memory pages with said memory pages distributed among said storage elements; and

access rights are defined on a sub-page basis.

7. A processing system comprising a plurality of interconnected processing cells that have at least one processor and at least one storage element, wherein:

said storage elements are configured to form a distributed main memory in which a plurality of memory pages reside, said memory pages being distributed among said storage elements with a number of memory pages being simultaneously held in a plurality of said storage elements; and

access rights are defined on a sub-page basis.

8. A processing system comprising a plurality of interconnected processing cells that have at least one processor and at least one storage element, wherein:

said storage elements are configured to form a distributed main memory for resident memory pages, said memory pages being distributed among said storage elements with a number of memory pages being simultaneously held in a plurality of said storage elements; and

access rights are defined on a sub-page basis.

9. A processing system comprising a plurality of interconnected processing cells that have at least one processor and at least one storage element operable as a cache, wherein:

said storage elements are configured to form a distributed main memory composed of a plurality of memory pages with said memory pages distributed among said storage elements; and

access rights are defined on a sub-page basis.