Method of analyzing static current test vectors for semiconductor integrated circuits

• US 6,694,495 B1
• Filed: 06/12/2001
• Issued: 02/17/2004
• Est. Priority Date: 09/28/2000
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Hussain, Hunaid, Ghosh, Pradipta
• Primary Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/879,506
• Time in Patent Office: 980 Days
• Field of Search: 716/4, 716/2, 716/18, 714/724
• US Class Current: 716/109
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation

Abstract

A method is provided for analyzing a test vector for use in measuring static current consumed by an integrated circuit that has an embedded memory device. According to the method, a potential test vector is applied to a functional model of the integrated circuit. The logic states of various nodes in the integrated circuit are detected in response to the potential test vector. At least some of the nodes correspond to the input address bits of the memory device, where the memory device has a valid address range on the input address bits. An output is produced for the potential test vector based on whether these logic states correspond to an address within the valid address range.

Claims

1. A method of analyzing a test vector for use in measuring static current consumed by an integrated circuit having at least one instance of an embedded memory device, the method comprising:

(a) applying a potential test vector to a functional model of the integrated circuit;

(b) detecting logic states of nodes in the integrated circuit corresponding to input address bits of the instance of the embedded memory device in response to applying the potential test vector, wherein the instance of the embedded memory device has a valid address range on the input address bits; and

(c) producing an output for the potential test vector based on whether the logic states detected in step (b) correspond to an address within the valid address range.

2. The method of claim 1 wherein step (c) comprises:

(c)(1) generating a log file for the potential test vector; and

(c)(2) producing a failure output in the log file for the potential test vector if the logic states detected in step (b) correspond to an address outside of the valid address range.

3. The method of claim 2 wherein step (c) further comprises:

(c)(3) producing a failure output in the log file for the potential test vector if any of the logic states of the address input bits detected in step (b) are unknown logic states.

4. The method of claim 2 wherein step (c) further comprises:

(c)(3) producing a failure output in the log file for the potential test vector if any of the logic states of the address input bits detected in step (b) are high impedance logic states.

5. The method of claim 1 and further comprising:

(d) identifying each instance of the memory device from a netlist of the integrated circuit, wherein the netlist includes a list of cells within the integrated circuit and interconnections between the cells;

(e) identifying the nodes in the netlist that correspond to the input address bits of each instance of the memory device that was identified in step (d); and

(f) generating a list of the nodes in the netlist for which the logic states will be detected in step (b), wherein the list includes all the nodes identified in step (e).

6. The method of claim 1 wherein:

step (a) comprises simulating a response of the functional model to the potential test vector with a computer software simulation program;

step (b) comprises outputting a value change dump file from the simulation program, which lists the logic state of each of the nodes at an instant in time when the functional model is in a substantially steady state; and

step (c) comprises inputting the value change dump file into a test vector analysis software program, comparing the states of the nodes corresponding to the input address bits to the valid address range and producing a failure output for the potential test vector if those logic states correspond to an address outside of the valid address range.

7. A computer readable medium comprising instructions readable by a programmable computer which, when executed, cause the computer to perform steps comprising:

(a) reading a computer file comprising logic states of nodes in a functional model of an integrated circuit, wherein the logic states correspond to a response of the model to a potential static current test vector;

(b) comparing the logic states of selected ones of the nodes that correspond to input address bits of an instance of an embedded memory device on the integrated circuit with a valid address range for that memory device; and

(c) producing an output for the potential test vector based on whether the logic states represent an address within the valid address range.

8. The computer readable medium of claim 7 wherein step (c) comprises:

(c)(1) generating a log file for the potential test vector; and

(c)(2) producing a failure output in the log file for the potential test vector if the logic states read from the computer file in step (a) correspond to an address outside of the valid address range.

9. The computer readable medium of claim 8 wherein step (c) further comprises:

(c)(3) producing a failure output in the log file for the potential test vector if any of the logic states of the address input bits are unknown logic states.

10. The computer readable medium of claim 8 wherein step (c) further comprises:

(c)(3) producing a failure output in the log file for the potential test vector if any of the logic states of the address input bits are high impedance logic states.

11. The computer readable medium of claim 7 wherein the instructions further cause the computer to perform steps comprising:

(d) applying the potential test vector to the functional model of the integrated circuit;

(e) detecting logic states of the nodes in the integrated circuit that correspond to the input address bits of the instance of the embedded memory device in response to applying the potential test vector; and

(f) outputting the logic states detected in step (e) to the computer file.

12. The computer readable medium of claim 11 wherein the instructions further cause the computer to perform steps comprising:

(g) identifying each instance of the embedded memory device from a netlist of the integrated circuit, wherein the netlist includes a list of cells within the integrated circuit and interconnections between the cells;

(h) identifying the nodes in the netlist that correspond to the input address bits of each instance of the memory device that was identified in step (f); and

(i) generating a list of the nodes in the netlist for which the logic states are detected in step (e), wherein the list includes all the nodes identified in step (h).

13. A computer-aided design tool for analyzing static current test vectors, the tool comprising:

means for reading a computer file comprising logic states of nodes in a functional model of an integrated circuit, wherein the logic states correspond to a response of the model to a potential static current test vector;

means for comparing the logic states of selected ones of the nodes that correspond to input address bits of an embedded memory device on the integrated circuit with a valid address range for that memory device; and

means for producing an output for the potential test vector based on whether the logic states represent an address within the valid address range.