Metal-gate electrode for CMOS transistor applications

• US 6,696,345 B2
• Filed: 01/07/2002
• Issued: 02/24/2004
• Est. Priority Date: 01/07/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert, Doyle, Brian, Doczy, Mark, Kavalieros, Jack
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): Rao, Shrinivas H.
• Application Number:
  US10/041,539
• Publication Number:
  US 20030129793A1
• Time in Patent Office: 778 Days
• Field of Search: 438/244, 438/592, 438/593, 438/594, 438/387, 438/491, 257/407, 257/408, 257/412, 257/413
• US Class Current: 438/387
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Described is a CMOS transistor structure with a multi-layered gate electrode structure and a method of fabrication. The gate electrode structure has a three-layered metallic gate electrode and a polysilicon layer. The first metallic layer acts as a barrier to prevent the second metallic layer from reacting with an underlying dielectric. The second metallic layer acts to set the work function of the gate electrode structure. The third metallic layer acts as a barrier to prevent the second metallic layer from reacting with the polysilicon layer.

The method of fabricating the gate electrode structure includes forming the three metallic layers thick enough that each layer provides the barrier and work-function setting functions mentioned above, but also thin enough that a subsequent wet-etch can be performed without excessive undercutting of the metallic layers. During implant and anneal processes, the polysilicon layer acts as a protective mask over the metallic layers to protect an underlying silicon substrate from interacting with dopants used during the implant process.

Claims

1. A method comprising:

forming a gate dielectric layer on a substrate;

depositing a first metallic layer on the gate dielectric layer;

depositing a second metallic layer on the first metallic layer wherein the second metallic layer has a conductivity and density of states higher than the first metallic layer; and

depositing a third metallic layer on the second metallic layer.

2. The method of claim 1 further comprising depositing a polysilicon layer on the third metallic layer.

3. The method of claim 1 further comprising:

etching the polysilicon layer; and

wet-etching the three metallic layers using the etched polysilicon for alignment.

4. The method of claim 3 further comprising ion implanting the substrate using the etched polysilicon as a mask.

5. A method of forming a metal gate electrode structure on a MOS transistor device comprising:

depositing a first metallic layer on a gate dielectric layer, the first metallic layer having a first work function;

depositing a second metallic layer on the first metallic layer wherein the first metallic layer is to act as a diffusion barrier between the second metallic layer and the gate dielectric layer, the second metallic layer having a second work function higher than the first work function of the first metallic layer;

depositing a third metallic layer on the second metallic layer;

depositing a polysilicon layer on the third metallic layer wherein the third metallic layer is to act as a silicidation barrier between the second metallic layer and the polysilicon layer; and

wet-etching the first, second, and third metallic layers with a wet etchant, wherein the first, second, and third metallic layers have sidewalls of a thickness smaller than a size of a beaded edge of the wet etchant so that the beaded edge of the wet-etchant cannot laterally cut into the sidewalls of the first, second and third metallic layers.

6. The method of claim 5 wherein the wet-etchant is formed by heating a 2:

1;

1 solution of H₂O;

H₂O₂;

H₂So₄ at a temperature of 70°

C. for 2 minutes.

7. The method of claim 5 further comprising dry-etching the polysilicon layer to form an etched polysilicon layer and using the etched polysilicon layer to align the wet-etching of the first, second and third metallic layers.

8. The method of claim 7 further comprising ion implanting the substrate using the etched polysilicon as a mask.

9. The method of comprising:

forming a gate dielectric layer on a substrate; and

forming a gate electrode to including three metallic layers above the dielectric layer.

10. The method of claim 9, further comprising forming the gate electrode to include a polysilicon layer.

11. The method of claim 9, wherein one of the metallic layers is a metal nitride.

12. The method of claim 9, including forming an n-type device and wherein one of the metallic layers comprises a work function of 4.11 eV±

0.2 eV.

13. The method of claim 9 including forming an p-type device and wherein one of the metallic layers comprises a work function of 5.2 eV±

0.2 eV.